Dan Gisselquist ZipCPU

ZipCPU / btncount.v

Last active November 20, 2018 15:31

	`default_nettype none
	//
	module btncount(i_clk, i_reset, i_btn, o_count);
	input wire i_clk, i_reset;
	input wire i_btn;
	output reg [31:0] o_count;

	reg last_btn;
	initial last_btn = 0;
	always @(posedge i_clk)

ZipCPU / mpy.json

Created November 15, 2018 20:44

	{signal: [
	{name: 'i_clk', wave: 'p..............'},
	{name: 'i_stb', wave: '0.1x...........'},
	{name: 'o_busy', wave: 'x.01........0..'},
	{name: 'i_a', wave: 'xx3x...........', data: ['0x34']},
	{name: 'i_b', wave: 'xx4x...........', data: ['0x25']},
	{},
	{name: 'r_a', wave: '0..3.......x...', data: ['8h34']},
	{name: 'r_b', wave: '0..4.......x...', data: ['8h25']},
	{name: 'acc', wave: '0..222222222xxx', data: ['0','0','0','x94','x94','x2e0','x780','x780','x780']},

ZipCPU / div.c

Last active November 9, 2018 17:51


	#define ITERATIONS_INV 2
	void ufp_inv(unsigned long *val) {
	unsigned long guess[PRECISION], dblbuf[PRECISION*2],
	sglbuf[PRECISION], two[PRECISION+1];
	int i, j;

	two[0] = HI_BIT;
	for(i=1; i<PRECISION+1; i++)
	two[i] = 0;

ZipCPU / changed.sby

Last active November 3, 2018 15:25

ZipCPU / clkgate.v

Last active October 18, 2018 15:00

	////////////////////////////////////////////////////////////////////////////////
	//
	// Filename: clkgate.v
	//
	// Project: A set of Yosys Formal Verification exercises
	//
	// Background: This file contains an implementation of a clock gate. The
	// clock should only tick if the enable line is high.
	//
	// Assume:

ZipCPU / Makefile

Last active October 18, 2018 14:31

	.PHONY: all
	all: blinky

	VERILATOR := verilator
	VERILATOR_ROOT ?= $(shell bash -c 'verilator -V\|grep VERILATOR_ROOT \| head -1 \| sed -e "s/^.=\s//"')
	VINC := $(VERILATOR_ROOT)/include

	obj_dir/Vblinky.cpp: blinky.v
	$(VERILATOR) -GWIDTH=12 --trace -Wall -cc blinky.v

ZipCPU / blinky.cpp

Created October 18, 2018 14:12

	#include <stdio.h>
	#include <stdlib.h>
	#include "Vblinky.h"
	#include "verilated.h"
	#include "verilated_vcd_c.h"

	void tick(int tickcount, Vblinky tb, VerilatedVcdC tfp) {
	tb->eval();
	if (tfp)
	tfp->dump(tickcount * 10 - 2);

ZipCPU / Xilinx demo code

Created October 8, 2018 03:08

	`default_nettype none

	`timescale 1 ns / 1 ps

	module myip_v1_0_S00_AXI #
	(
	// Users to add parameters here

	// User parameters ends
	// Do not modify the parameters beyond this line

ZipCPU / test.v

Created July 19, 2018 00:20

	`default_nettype none
	//
	module test(i_clk, i_value, o_value);
	input wire i_clk;
	input wire [15:0] i_value;
	output reg [15:0] o_value;

	wire [15:0] pre_value;
	assign pre_value = i_value + 1;

ZipCPU / boxcar_tb.txt

Created July 16, 2018 16:16

Boxcar output when working