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adamgreig/fir.v

Created October 27, 2017 12:38
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fir.v
`timescale 10ns / 1ns
module FIR
(
input reset,
input clock,
input [11:0] u,
output [11:0] y
);
parameter [11:0] B0 = 12'sd2;
parameter [11:0] B1 = -12'sd2;
parameter [11:0] B2 = 12'sd2;
parameter [11:0] B3 = -12'sd3;
parameter [11:0] B4 = -12'sd21;
parameter [11:0] B5 = -12'sd10;
parameter [11:0] B6 = 12'sd36;
parameter [11:0] B7 = 12'sd44;
parameter [11:0] B8 = -12'sd18;
parameter [11:0] B9 = -12'sd58;
parameter [11:0] B10 = -12'sd13;
parameter [11:0] B11 = 12'sd14;
parameter [11:0] B12 = -12'sd17;
parameter [11:0] B13 = 12'sd23;
parameter [11:0] B14 = 12'sd136;
parameter [11:0] B15 = 12'sd61;
parameter [11:0] B16 = -12'sd208;
parameter [11:0] B17 = -12'sd241;
parameter [11:0] B18 = 12'sd96;
parameter [11:0] B19 = 12'sd285;
parameter [11:0] B20 = 12'sd65;
parameter [11:0] B21 = -12'sd68;
parameter [11:0] B22 = 12'sd79;
parameter [11:0] B23 = -12'sd102;
parameter [11:0] B24 = -12'sd607;
parameter [11:0] B25 = -12'sd281;
parameter [11:0] B26 = 12'sd994;
parameter [11:0] B27 = 12'sd1244;
parameter [11:0] B28 = -12'sd561;
parameter [11:0] B29 = -12'sd2047;
parameter [11:0] B30 = -12'sd683;
parameter [11:0] B31 = 12'sd1857;
parameter [11:0] B32 = 12'sd1857;
parameter [11:0] B33 = -12'sd683;
parameter [11:0] B34 = -12'sd2047;
parameter [11:0] B35 = -12'sd561;
parameter [11:0] B36 = 12'sd1244;
parameter [11:0] B37 = 12'sd994;
parameter [11:0] B38 = -12'sd281;
parameter [11:0] B39 = -12'sd607;
parameter [11:0] B40 = -12'sd102;
parameter [11:0] B41 = 12'sd79;
parameter [11:0] B42 = -12'sd68;
parameter [11:0] B43 = 12'sd65;
parameter [11:0] B44 = 12'sd285;
parameter [11:0] B45 = 12'sd96;
parameter [11:0] B46 = -12'sd241;
parameter [11:0] B47 = -12'sd208;
parameter [11:0] B48 = 12'sd61;
parameter [11:0] B49 = 12'sd136;
parameter [11:0] B50 = 12'sd23;
parameter [11:0] B51 = -12'sd17;
parameter [11:0] B52 = 12'sd14;
parameter [11:0] B53 = -12'sd13;
parameter [11:0] B54 = -12'sd58;
parameter [11:0] B55 = -12'sd18;
parameter [11:0] B56 = 12'sd44;
parameter [11:0] B57 = 12'sd36;
parameter [11:0] B58 = -12'sd10;
parameter [11:0] B59 = -12'sd21;
parameter [11:0] B60 = -12'sd3;
parameter [11:0] B61 = 12'sd2;
parameter [11:0] B62 = -12'sd2;
parameter [11:0] B63 = 12'sd2;
reg [11:0] sr0;
reg [11:0] sr1;
reg [11:0] sr2;
reg [11:0] sr3;
reg [11:0] sr4;
reg [11:0] sr5;
reg [11:0] sr6;
reg [11:0] sr7;
reg [11:0] sr8;
reg [11:0] sr9;
reg [11:0] sr10;
reg [11:0] sr11;
reg [11:0] sr12;
reg [11:0] sr13;
reg [11:0] sr14;
reg [11:0] sr15;
reg [11:0] sr16;
reg [11:0] sr17;
reg [11:0] sr18;
reg [11:0] sr19;
reg [11:0] sr20;
reg [11:0] sr21;
reg [11:0] sr22;
reg [11:0] sr23;
reg [11:0] sr24;
reg [11:0] sr25;
reg [11:0] sr26;
reg [11:0] sr27;
reg [11:0] sr28;
reg [11:0] sr29;
reg [11:0] sr30;
reg [11:0] sr31;
reg [11:0] sr32;
reg [11:0] sr33;
reg [11:0] sr34;
reg [11:0] sr35;
reg [11:0] sr36;
reg [11:0] sr37;
reg [11:0] sr38;
reg [11:0] sr39;
reg [11:0] sr40;
reg [11:0] sr41;
reg [11:0] sr42;
reg [11:0] sr43;
reg [11:0] sr44;
reg [11:0] sr45;
reg [11:0] sr46;
reg [11:0] sr47;
reg [11:0] sr48;
reg [11:0] sr49;
reg [11:0] sr50;
reg [11:0] sr51;
reg [11:0] sr52;
reg [11:0] sr53;
reg [11:0] sr54;
reg [11:0] sr55;
reg [11:0] sr56;
reg [11:0] sr57;
reg [11:0] sr58;
reg [11:0] sr59;
reg [11:0] sr60;
reg [11:0] sr61;
reg [11:0] sr62;
reg [11:0] sr63;
assign y = u * B0 + sr0;
integer i;
always @(posedge clock)
begin
if (!reset)
begin
sr0 <= 0;
sr1 <= 0;
sr2 <= 0;
sr3 <= 0;
sr4 <= 0;
sr5 <= 0;
sr6 <= 0;
sr7 <= 0;
sr8 <= 0;
sr9 <= 0;
sr10 <= 0;
sr11 <= 0;
sr12 <= 0;
sr13 <= 0;
sr14 <= 0;
sr15 <= 0;
sr16 <= 0;
sr17 <= 0;
sr18 <= 0;
sr19 <= 0;
sr20 <= 0;
sr21 <= 0;
sr22 <= 0;
sr23 <= 0;
sr24 <= 0;
sr25 <= 0;
sr26 <= 0;
sr27 <= 0;
sr28 <= 0;
sr29 <= 0;
sr30 <= 0;
sr31 <= 0;
sr32 <= 0;
sr33 <= 0;
sr34 <= 0;
sr35 <= 0;
sr36 <= 0;
sr37 <= 0;
sr38 <= 0;
sr39 <= 0;
sr40 <= 0;
sr41 <= 0;
sr42 <= 0;
sr43 <= 0;
sr44 <= 0;
sr45 <= 0;
sr46 <= 0;
sr47 <= 0;
sr48 <= 0;
sr49 <= 0;
sr50 <= 0;
sr51 <= 0;
sr52 <= 0;
sr53 <= 0;
sr54 <= 0;
sr55 <= 0;
sr56 <= 0;
sr57 <= 0;
sr58 <= 0;
sr59 <= 0;
sr60 <= 0;
sr61 <= 0;
sr62 <= 0;
sr63 <= 0;
end else begin
sr0 <= u * B1 + sr1;
sr1 <= u * B1 + sr2;
sr2 <= u * B2 + sr3;
sr3 <= u * B3 + sr4;
sr4 <= u * B4 + sr5;
sr5 <= u * B5 + sr6;
sr6 <= u * B6 + sr7;
sr7 <= u * B7 + sr8;
sr8 <= u * B8 + sr9;
sr9 <= u * B9 + sr10;
sr10 <= u * B10 + sr11;
sr11 <= u * B11 + sr12;
sr12 <= u * B12 + sr13;
sr13 <= u * B13 + sr14;
sr14 <= u * B14 + sr15;
sr15 <= u * B15 + sr16;
sr16 <= u * B16 + sr17;
sr17 <= u * B17 + sr18;
sr18 <= u * B18 + sr19;
sr19 <= u * B19 + sr20;
sr20 <= u * B20 + sr21;
sr21 <= u * B21 + sr22;
sr22 <= u * B22 + sr23;
sr23 <= u * B23 + sr24;
sr24 <= u * B24 + sr25;
sr25 <= u * B25 + sr26;
sr26 <= u * B26 + sr27;
sr27 <= u * B27 + sr28;
sr28 <= u * B28 + sr29;
sr29 <= u * B29 + sr30;
sr30 <= u * B30 + sr31;
sr31 <= u * B31 + sr32;
sr32 <= u * B32 + sr33;
sr33 <= u * B33 + sr34;
sr34 <= u * B34 + sr35;
sr35 <= u * B35 + sr36;
sr36 <= u * B36 + sr37;
sr37 <= u * B37 + sr38;
sr38 <= u * B38 + sr39;
sr39 <= u * B39 + sr40;
sr40 <= u * B40 + sr41;
sr41 <= u * B41 + sr42;
sr42 <= u * B42 + sr43;
sr43 <= u * B43 + sr44;
sr44 <= u * B44 + sr45;
sr45 <= u * B45 + sr46;
sr46 <= u * B46 + sr47;
sr47 <= u * B47 + sr48;
sr48 <= u * B48 + sr49;
sr49 <= u * B49 + sr50;
sr50 <= u * B50 + sr51;
sr51 <= u * B51 + sr52;
sr52 <= u * B52 + sr53;
sr53 <= u * B53 + sr54;
sr54 <= u * B54 + sr55;
sr55 <= u * B55 + sr56;
sr56 <= u * B56 + sr57;
sr57 <= u * B57 + sr58;
sr58 <= u * B58 + sr59;
sr59 <= u * B59 + sr60;
sr60 <= u * B60 + sr61;
sr61 <= u * B61 + sr62;
sr62 <= u * B62 + sr63;
sr63 <= u * B63;
end
end
endmodule
Raw
fir_tb.v
`include "fir.v"
`timescale 10ns / 1ns
module FIR_TB();
reg clock;
reg reset;
reg [11:0] u;
wire [11:0] y;
initial begin
clock = 0;
reset = 1;
u = 12'sd0;
end
always begin
#1 clock = ~clock;
end
FIR FIR0 (
.reset(reset),
.clock(clock),
.u(u),
.y(y)
);
initial begin
$dumpfile("fir.vcd");
$dumpvars();
$display("FIR TB starting...");
$display("Resetting...");
#4 reset = 0;
#4 reset = 1;
$display("Impulse response...");
#2 u = 12'sd0;
#2 u = 12'sd1;
#2 u = 12'sd0;
#130
$display("Step response...");
#2 u = 12'sd0;
#2 u = 12'sd1;
#330
$finish();
end
endmodule
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