newfile.v

newfile.v

`default_nettype none
`include "hvsync_generator.v"

module top(clk, reset, hsync, vsync, rgb);

  input clk, reset;
  output reg hsync, vsync;
  output reg [2:0] rgb;
  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;

  wire hsync0, vsync0;
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(reset),
    .hsync(hsync0),
    .vsync(vsync0),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );
  
  // delay 1 clk
  always @(posedge clk)
    { hsync, vsync } <= { hsync0, vsync0 };
  
  // init
  reg sel = 0;

  //-- En flanco de subida sacamos un "1" por la salida
  always @(posedge(clk))
    sel <= 1;

  reg [5:0] row = 0;
  wire [63:0] data;
  
  wire pixel_on;
  image image0 (
    // read ports
    .clk( clk ),
    .row( hpos[8:3] ),
    .col( vpos[8:3] ),
    .data( pixel_on ),
    // write ports
    .rowW( row ),
    .dataW( data )
  );
  
  parameter RULE = 126;
  parameter SEED = 64'b10000000000000000000000000000000000000000; // seed for first line

  wire [7:0] w_rule;
  assign w_rule = RULE;

  wire [63:0] rin;
  automaton #(.WIDTH(64)) AUTOMATON ( .in(data), .rule(w_rule), .out(rin));

  assign data = (sel == 0) ? SEED : rout;

  reg [63:0] rout;
    
  always @(posedge(clk))
  begin
    row <= (row == 59) ? 0 : ( row + 1 );
    rout <= rin; // Pasamos la salida del Cellular Automaton a la salida del registro en cada positive edge
  end
  
  assign rgb = {pixel_on,pixel_on,pixel_on};
  
endmodule

module image (
  // Read ports:
  input wire clk,
  input wire [5:0] row,
  input wire [5:0] col,
  output reg data,
  // Write ports
  input wire [5:0] rowW,  // line number we write
  input wire [63:0] dataW // full 80 bits of the line
  );

  // 60 rows of 64 bits
  reg [63:0] rom [0:59];

  // Read Rom Logic
  always @(posedge clk) begin
    data <= rom[row][col];
  end

  //reg [6:0] counter = 0;

  // Write logic
  always @(posedge clk) begin
    if (rowW != row) begin // don't write rowW if we are reading the same row.
      rom [rowW] <= dataW;
    end
  end

endmodule

module automaton #(parameter WIDTH = 8)
  ( input wire [WIDTH-1:0] in,
    input wire [7:0] rule,
    output wire [WIDTH-1:0] out
  );

  genvar i;
  generate
    for (i=0; i<WIDTH; i=i+1)
    begin : automaton_cell
      automaton_cell acell ( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, rule, out[i] );
    end
  endgenerate

endmodule

module automaton_cell(in, rule, out);
    input wire[2:0] in;
    input wire[7:0] rule;

    output wire out;

    assign out = rule[in];
endmodule