Binary Division by 3 in RPL

div3.rpl

<<
R->B 256 *
DUP DUP DUP DUP
4 /
SWAP 16 /
3 ROLL 64 /
4 ROLL 256 /
5 ROLL 1024 /
+ + + +
128 / DUP
# 1b AND
SWAP
2 /
+
B->R
>>

div3_mod3.vh

// Binary Division by 3 in Verilog
function automatic [7:0] div3;
  input [7:0] x;
  reg [15:0] a, t ;
  begin
    a = { x, 8'b0 };
    t = (a>>2) + (a>>4) + (a>>6) + (a>>8) + (a>>10) ;
    div3 = t[15:8] + { 7'b0, t[7] };
  end
endfunction

// Binary modulo 3
function automatic [1:0] mod3;
  input [7:0] x;
  begin
    mod3=0;
    case ( 2*(x[7]+x[5]+x[3]+x[1])+(x[6]+x[4]+x[2]+x[0]) )
      0,3,6,9,12: mod3=0;
      1,4,7,10  : mod3=1;
      2,5,8,11  : mod3=2;
    endcase
  end
endfunction