toy-sandbox.v

module vga_demo(/*AUTOARG*/);
    input clk50m;
    input reset_n;

    output hsync_n;
    output vsync_n;
    output data_enable;
    output pixel_clk;
    output [7:0] r;
    output [7:0] g;
    output [7:0] b;

    parameter pixel_freq = "27 MHz";

    parameter h_bits = 10;
    parameter h_visible = 720;
    parameter h_front = 18;
    parameter h_sync = 61;
    parameter h_back = 58;

    parameter v_bits = 10;
    parameter v_visible = 480;
    parameter v_front = 9;
    parameter v_sync = 5;
    parameter v_back = 30;

    altera_pll #(.pll_type("General"),
                 .pll_subtype("General"),
                 .fractional_vco_multiplier("false"),
                 .reference_clock_frequency("50.0 MHz"),
                 .operation_mode("normal"),
                 .number_of_clocks(1),
                 .output_clock_frequency0(pixel_freq),
                 .phase_shift0("0 ps"),
                 .duty_cycle0(50))
    pixelpll (.rst(~reset_n),
              .refclk(clk50m),
              .fbclk(0),
              .outclk(pixel_clk));

    reg [h_bits-1:0] h;
    reg [v_bits-1:0] v;

    always @(posedge pixel_clk or negedge reset_n) begin
        if (~reset_n) begin
            h <= 0;
            v <= 0;
        end else begin
            if (h < h_visible + h_front + h_sync + h_back - 1) begin
                h <= h + 1;
            end else begin
                h <= 0;
                if (v < v_visible + v_front + v_sync + v_back - 1) begin
                    v <= v + 1;
                end else begin
                    v <= 0;
                end
            end
        end
    end

    assign hsync_n = ~((h_visible + h_front <= h) && (h < h_visible + h_front + h_sync));
    assign vsync_n = ~((v_visible + v_front <= v) && (v < v_visible + v_front + v_sync));
    assign data_enable = (h < h_visible) && (v < v_visible);

    assign r = h[0:7];
    assign g = v[0:7];
    assign b = h ^ v;
endmodule