agrif

module reservoir_node_0(input enable,
                         input [0:99] r,
                         input [0:15] u,
                         output out);
    wire value = r[18] & r[72]
               | r[18] & ~u[13]
               | r[72] & ~u[13]
               | r[18] & ~r[92] & ~u[15]
               | r[18] & ~r[92] & ~u[8]
               | r[18] & ~u[15] & ~u[8]

agrif

#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>

#include "font.h"

__sfr __at 0x50 ioLED;

agrif

module vga_demo(/*AUTOARG*/);
    input clk50m;
    input reset_n;

    output hsync_n;
    output vsync_n;
    output data_enable;
    output pixel_clk;
    output [7:0] r;
    output [7:0] g;

agrif

#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>

__sfr __at 0x00 ioLED;

__sfr __at 0x10 ioID0;
__sfr __at 0x11 ioID1;
__sfr __at 0x12 ioID2;

agrif

module tv80_avalon_master(/*AUTOARG*/);
    parameter width = 16;

    // clock and reset
    input clk;
    input reset_n;

    // avalon master signals
    output [width-1:0] address;
    output reg read_n;

agrif

#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>

__sfr __at 0x00 ioLED;

__sfr __at 0x10 ioID0;
__sfr __at 0x11 ioID1;
__sfr __at 0x12 ioID2;

agrif

#include <stdbool.h>
#include <stdint.h>

__sfr __at 0x00 ioLED;

__sfr __at 0x10 ioID0;
__sfr __at 0x11 ioID1;
__sfr __at 0x12 ioID2;
__sfr __at 0x13 ioID3;
__sfr __at 0x14 ioID4;

agrif

import inspect

## utility stuff

def identity(x):
    return x

def swap(t):
    return tuple(reversed(t))

agrif

    ld a, 1
loop:
    nop
    out (0), a                  ; LEDs are on port 0
    inc a
    jr loop

agrif

lex = Lexer()
lex['WS'] = regex.compile(r'\s+')
lex.ignore('WS')
lex['N'] = regex.compile(r'\d+')
for c in '+*()':
    lex[c] = c

class MathBuilder(Builder):
    """
    e.wrap -> t;