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esynr3z / !readme.md
Last active March 16, 2025 14:44
Obfuscate Verilog/SystemVerilog code

Basics

Use Verible Code Obfuscator for obfuscation.

Obfuscate foo.v and save dictionary with all replacements:

verible-verilog-obfuscate --save_map obf.map < foo.v > foo_obf.v