Out-of-SSA fib example

gistfile1.txt

: fib ( a -- b b )
    { fixnum } declare [ 0 1 ] dip [ [ + ] keep swap >fixnum ] times ;

After tweaking ##parallel-copy live-ranges, we get the following out-of-SSA CFG (I've taken the liberty of renaming the vregs per the leader-map):

=== word: fib, label: fib

=== Basic block #0

##safepoint
##prologue
##branch

Successors: 1

=== Basic block #1

##inc-d 3
##peek 48 D 3
##sar-imm 48 48 4
##load-integer 23 0
##load-integer 24 1
##branch

Successors: 2

=== Basic block #2

##copy 55 23 int-rep
##branch

Successors: 5

=== Basic block #3

##add 23 23 24
##add-imm 55 55 1
##safepoint
##branch

Successors: 4

=== Basic block #4

##copy 60 24 int-rep
##copy 24 23 int-rep
##copy 23 60 int-rep
##branch

Successors: 5

=== Basic block #5

##compare-integer-branch 55 48 cc<

Successors: 3, 6

=== Basic block #6

##inc-d -2
##shl-imm 23 23 4
##replace 23 D 1
##shl-imm 24 24 4
##replace 24 D 0
##branch

Successors: 7

=== Basic block #7

##safepoint
##epilogue
##return

=== stack frame: f

But the CFG can't be finalized yet, because there's a bad-vreg error during the linear-scan pass.