- Commonly used in semiconductor design today
- Supported by more than one EDA vendor
- Not a subset of or derived from any other format (so Verilog/UVM don’t make the cut, for example)
- Note: GDSII is not included because it is essentially superseded by OASIS format, which is very similar
| Type | Name | Developer | Free? | Common File Extensions | OSS Repo |
|---|---|---|---|---|---|
| Digital Design Specification | SystemC | Accellera/IEEE | Yes | .c, .cpp, .cc, .h, .hpp, .hh | Accellera Official SystemC |
| Digital Design Specification | SystemVerilog (SV) | IEEE | Yes | .v, .vl, .vg, .sv, .vh, .svh, .svp | Slang |
| Digital Design Specification | VHSIC Hardware Description Language (VHDL) | IEEE | Yes | .vhd, .vhdl, .vho | GHDL |
| Digital Design Interface Specification | IP-XACT | IEEE | Yes | .xml | PeakRDL |
| Digital Design Interface Specification | SystemRDL | Accellera | Yes | .rdl | PeakRDL |
| Digital Design Interface Specification | Liberty | Synopsys | Yes | .lib | Synopsys Liberty Parser |
| Digital Simulation Output | Value Change Dump (VCD) | IEEE | Yes | .vcd | GTKWave |
| Digital Simulation Output | Switching Activity Interchange Format (SAIF) | IEEE | Yes | .saif | OpenSTA |
| Digital Simulation Output | Standard Delay Format (SDF) | IEEE | Yes | .sdf | OpenSTA |
| Digital Design Constraints | Synopsys Design Constraints (SDC) | Synopsys | Yes | .sdc | OpenSTA |
| Digital Design Constraints | Unified Power Format (UPF) | IEEE | Yes | .upf | OpenROAD (incomplete) |
| Physical Design | Interconnect Technology Format (ITF) | Synopsys | Yes | .itf, .tf | N/A |
| Physical Design | OpenAccess (OA) | Si2 | No ($) | .oa | N/A |
| Physical Design | Standard Parasitic Exchange Format (SPEF) | IEEE | Yes | .spef | OpenSTA |
| Physical Design | Open Artwork System Interchange Standard (OASIS) | SEMI | No ($) | .oas | LibrEDA OASIS |
| Physical Design | Library Exchange Format (LEF) | Si2 | Yes | .lef | Si2 LEF-DEF Parser |
| Physical Design | Design Exchange Format (DEF) | Si2 | Yes | .def | Si2 LEF-DEF Parser |
| Analog Design Specification | Simulation Program with Integrated Circuit Emphasis (SPICE) | UC Berkeley | Yes | .ckt, .sp, .net, .cir, .scs, .mod, .mdl, .lib, .sub, .eldo | Ngspice |
| Analog Design Specification | Verilog-AMS | Accellera | Yes | .va, .vams | OpenVAF |