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VLSI/EDA Popular Standard Design Formats
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vlsi-eda-std-formats.md

VLSI/EDA Common Standard Design Formats/Languages

Criteria for Inclusion

  • Commonly used in semiconductor design today
  • Supported by more than one EDA vendor
  • Not a subset of or derived from any other format (so Verilog/UVM don’t make the cut, for example)
  • Note: GDSII is not included because it is essentially superseded by OASIS format, which is very similar

Table

Type Name Developer Free? Common File Extensions URL OSS Repo URL
Digital Design Specification SystemC Accelera/IEEE Yes .c, .cpp, .cc, .h, .hpp, .hh https://www.accellera.org/downloads/standards/systemc https://github.com/accellera-official/systemc
Digital Design Specification SystemVerilog (SV) IEEE Yes .v, .vl, .vg, .sv, .vh, .svh, .svp https://standards.ieee.org/ieee/1800/7743/ https://github.com/MikePopoloski/slang
Digital Design Specification VHSIC Hardware Description Language (VHDL) IEEE Yes .vhd, .vhdl, .vho https://ieeexplore.ieee.org/document/8938196 https://github.com/ghdl/ghdl
Digital Design Interface Specification IP-XACT IEEE Yes .xml https://standards.ieee.org/ieee/1685/10583/ https://github.com/SystemRDL/PeakRDL
Digital Design Interface Specification Liberty Synopsys Yes .lib https://www.synopsys.com/community/interoperability-programs/tap-in.html https://github.com/eclufsc/libertyParser
Digital Simulation Output Switching Activity Interchange Format (SAIF) IEEE Yes .saif https://standards.ieee.org/ieee/1801/6767/ https://github.com/parallaxsw/OpenSTA/tree/master/power
Digital Simulation Output Standard Delay Format (SDF) IEEE Yes .sdf https://standards.ieee.org/ieee/1497/2235/ https://github.com/parallaxsw/OpenSTA/tree/master/sdf
Digital Simulation Output Value Change Dump (VCD) IEEE Yes .vcd https://standards.ieee.org/ieee/1800/7743/ https://github.com/ben-marshall/verilog-vcd-parser
Digital Design Constraints Synopsys Design Constraints (SDC) Synopsys Yes .sdc https://www.synopsys.com/community/interoperability-programs/tap-in.html https://github.com/parallaxsw/OpenSTA/tree/master/sdc
Digital Design Constraints Unified Power Format (UPF) IEEE Yes .upf https://standards.ieee.org/ieee/1801/6767/ ???
PDK Interconnect Technology Format (ITF) Synopsys Yes .itf, .tf https://www.synopsys.com/community/interoperability-programs/tap-in.html ???
Physical Design OpenAccess (OA) Si2 No ($) .oa https://si2.org/openaccess-coalition/ N/A
Physical Design Standard Parasitic Exchange Format (SPEF) IEEE Yes .spef https://standards.ieee.org/ieee/1481/7651/ https://github.com/parallaxsw/OpenSTA/tree/master/parasitics
Physical Design Open Artwork System Interchange Standard (OASIS) SEMI No ($) .oas https://store-us.semi.org/products/p03800-semi-p39-specification-for-oasis%C2%AE-open-artwork-system-interchange-standard https://codeberg.org/LibrEDA/libreda-oasis
Physical Design Library Exchange Format (LEF) Si2 Yes .lef https://si2.org/lef-def-downloads/ https://github.com/asyncvlsi/lefdef
Physical Design Design Exchange Format (DEF) Si2 Yes .def https://si2.org/lef-def-downloads/ https://github.com/asyncvlsi/lefdef
Analog Design Specification Simulation Program with Integrated Circuit Emphasis (SPICE) UC Berkeley Yes .ckt, .sp, .net, .cir, .scs, .mod, .mdl, .lib, .sub, .eldo https://github.com/hedhyw/spice3f5 https://github.com/hedhyw/spice3f5
Analog Design Specification Verilog-AMS Accelera Yes .va, .vams https://www.accellera.org/downloads/standards/v-ams https://github.com/pascalkuthe/OpenVAF
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