allexoll

package vexriscv.plugin.riscvdebug

import spinal.core._
import spinal.lib._
import spinal.lib.blackbox.xilinx.s7.{BSCANE2, BUFG}
import spinal.lib.com.jtag._


/**
 * Creates a DTM similat to the JTAG DTM, but mapped to BSCANE2 USER1/2/3

allexoll

package vexriscv.plugin.riscvdebug

import spinal.core._
import spinal.lib._
import spinal.lib.blackbox.xilinx.s7.BUFG
import spinal.lib.com.jtag._

/*
riscv-debug-stable.pdf chapter 6.1
Debug Transport Modules provide access to the DM over one or more transports (e.g. JTAG or USB)

allexoll

#!/usr/bin/python3
import os
import shutil
import subprocess
import sys
import logging
import shlex

logger = logging.getLogger(__name__)
symbiflow_init = 'bash -lec {}'

allexoll

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  <vendor>NXP Semiconductors</vendor>
  <vendorID>NXP</vendorID>
  <name>LPC845</name>
  <series>LPC</series>
  <version>1.6</version>
  <description>LPC845 NXP Microcontroller</description>
  <licenseText>Copyright 2016-2020 NXP\n All rights reserved.\n SPDX-License-Identifier: BSD-3-Clause</licenseText>
  <cpu>

allexoll

  // from a jtag main standpoint. the jtag debugger either updates(write to) the DR, or captures it (read from)
  def readAndWrite[T<: Data](captureData: T, updateData: T, captureReady: Bool, updateValid:Bool)(instructionId: Int) = {
    val area = new JtagTapInstructionReadWrite(captureData, updateData, captureReady)
    map(area.ctrl, instructionId)
    updateValid := RegNext(area.ctrl.enable && area.ctrl.update)
    area
  }

/**
 * Usefull to create a jtag tap instruction that has a different data input/output, with a captureReady

allexoll

object Apb3Decoder{

  def getOutputConfig(inputConfig: Apb3Config, decodings: Seq[SizeMapping]) = inputConfig.copy(selWidth = decodings.size)

  def apply(inputConfig: Apb3Config, decodings: Seq[SizeMapping]): Apb3Decoder = new Apb3Decoder(inputConfig, decodings)

  def apply(master: Apb3, slaves: Seq[(Apb3, SizeMapping)]): Apb3Decoder = {

    // proposal
    for(slave <- slaves)

allexoll

package SolSoc.lib
import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
import spinal.lib.com.eth.{MacEth, MacEthParameter, Mii, MiiParameter, MiiRxParameter, MiiTxParameter, PhyIo}


object Apb3MacEthConfig{
  def getApb3Config = Apb3Config(
    addressWidth = 6,

allexoll

- peripheral:
    groupName: SPIXDR
    description: Management Data Input Output
    registers:
      - register:
        - name: DATA
          description: Data register
          addressOffset: 0x00
          fields:
            - field:

allexoll

#define .score r1
#define .var0 r2
#define .var1 r3
#define .count_0 r4
#define .count_1 r5
#define .count_2 r6
#define .head_x r7
#define .head_y r8
#define .tail_x r9
#define .tail_y r10

allexoll

  Running `/Users/allexoll/Desktop/probe-rs/target/release/probe-rs-cli --version`
Probe-rs CLI 0.10.0
⋊> ~/D/p/cli on master ⨯ cargo run --release -- info                    22:59:31
    Finished release [optimized + debuginfo] target(s) in 0.27s
     Running `/Users/allexoll/Desktop/probe-rs/target/release/probe-rs-cli info`
⋊> ~/D/p/cli on master ⨯ RUST_LOG=trace cargo run --release -- info     22:59:45
    Finished release [optimized + debuginfo] target(s) in 0.15s
     Running `/Users/allexoll/Desktop/probe-rs/target/release/probe-rs-cli info`
 DEBUG jaylink > libusb 1.0.24.11584
 DEBUG jaylink > libusb has capability API: true