Generate 7-bit sin table for FPGA/Verilog

gen_sin_table_fpga.py

import math

for i in range(16):
    print(
        f"@{(i*16):08x} "
        + " ".join(f"{int(-math.cos((j+i*16)*math.pi*2/255)*127.1+128):02x}" for j in range(16))
    )

# for Xilinx Vivado FPGA purposes
# sin_table.mem

"""
@00000000 00 00 01 01 01 01 02 02 03 04 04 05 06 07 08 09
@00000010 0a 0b 0d 0e 10 11 13 14 16 18 1a 1c 1d 1f 22 24
@00000020 26 28 2a 2d 2f 32 34 37 39 3c 3f 41 44 47 4a 4d
@00000030 4f 52 55 58 5b 5e 61 64 67 6a 6e 71 74 77 7a 7d
@00000040 80 83 87 8a 8d 90 93 96 99 9c 9f a2 a5 a8 ab ae
@00000050 b1 b4 b7 ba bc bf c2 c4 c7 ca cc cf d1 d3 d6 d8
@00000060 da dc de e1 e3 e4 e6 e8 ea ec ed ef f0 f2 f3 f4
@00000070 f5 f7 f8 f9 fa fa fb fc fc fd fd fe fe fe ff ff
@00000080 ff ff fe fe fe fd fd fc fc fb fa fa f9 f8 f7 f5
@00000090 f4 f3 f2 f0 ef ed ec ea e8 e6 e4 e3 e1 de dc da
@000000a0 d8 d6 d3 d1 cf cc ca c7 c4 c2 bf bc ba b7 b4 b1
@000000b0 ae ab a8 a5 a2 9f 9c 99 96 93 90 8d 8a 87 83 80
@000000c0 7d 7a 77 74 71 6e 6a 67 64 61 5e 5b 58 55 52 4f
@000000d0 4d 4a 47 44 41 3f 3c 39 37 34 32 2f 2d 2a 28 26
@000000e0 24 22 1f 1d 1c 1a 18 16 14 13 11 10 0e 0d 0b 0a
@000000f0 09 08 07 06 05 04 04 03 02 02 01 01 01 01 00 00
"""