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/* | |
* Verilog Simulator checker by predefined macro. | |
* | |
* Copyright (C) 2017 MURAMATSU Atsushi <[email protected]> | |
* | |
* Permission is hereby granted, free of charge, to any person | |
* obtaining a copy of this software and associated documentation files | |
* (the "Software"), to deal in the Software without restriction, | |
* including without limitation the rights to use, copy, modify, merge, | |
* publish, distribute, sublicense, and/or sell copies of the Software, | |
* and to permit persons to whom the Software is furnished to do so, | |
* subject to the following conditions: | |
* | |
* The above copyright notice and this permission notice shall be | |
* included in all copies or substantial portions of the Software. | |
* | |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE | |
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
*/ | |
module PREDEF; | |
initial begin | |
`ifdef VCS | |
$display("Synopsis VCS"); | |
`endif | |
`ifdef INCA | |
$display("Cadence NC-Verilog"); | |
`endif | |
`ifdef MODEL_TECH | |
$display("Mentor Graphics ModelSIM/Questa"); | |
`endif | |
`ifdef XILINX_ISIM | |
$display("Xilinx ISE Simulator"); | |
`endif | |
`ifdef XILINX_SIMULATOR | |
$display("Xilinx Vivado Simulator"); | |
`endif | |
`ifdef __ICARUS__ | |
$display("Icarus Verilog <http://iverilog.icarus.com>"); | |
`endif | |
`ifdef VERILATOR | |
$display("Verilator <https://www.veripool.org/wiki/verilator>"); | |
`endif | |
`ifdef Veritak | |
$display("Veritak <http://www.sugawara-systems.com>"); | |
`endif | |
end // initial begin | |
endmodule // PREDEF | |
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