andrewsclapp

_TIM4_IRQHandler:
        ; patch test - turn on 1's digit
        BSET PB_ODR,#0
        ; end patch test

        ; TIM4 interrupt handler for software Rx/Tx
        BRES    TIM4_SR,#0      ; clear TIM4 UIF

        LD      A,TIM4RCNT      ; test receive step counter
        JREQ    TIM4_TESTTRANS  ; nothing to do - check for transmit

andrewsclapp

transmit side:

: send_byte ( n -- )  \ send byte as 8 bits
    ' TXP! 'EMIT !
    8 .R
    ' EMIT 'EMIT !
;

VARIABLE STATE
VARIABLE REM

andrewsclapp

\res MCU: STM8S103
\res export PA_ODR PA_DDR PA_CR1

#require WIPE
#require ]B!
\ #require 'IDLE

NVM

: INIT

andrewsclapp

\res MCU: STM8S103
\res export PA_ODR PA_DDR PA_CR1
\res export PB_ODR PB_DDR PB_CR1
\res export PC_ODR PC_DDR PC_CR1
\res export PD_ODR PD_DDR PD_CR1
\res export PE_ODR PE_DDR PE_CR1
\res export PF_ODR PF_DDR PF_CR1

#require lib/]B!
#require target/WIPE

andrewsclapp

\ ADC single scan mode 1 channel at a time

\res MCU: STM8L051
\res export CLK_PCKENR2 ADC1_CR1 ADC1_CR2 ADC1_CR3
\res export RI_ASCR1 RI_IOSR2
\res export ADC1_SQR1 ADC1_SQR2 ADC1_SQR3 ADC1_SQR4
\res export ADC1_DRH ADC1_DRL
\res export ADC1_SR

#require ]B!

andrewsclapp

\ select the (STM8S) controller first (alt. STM8S105. STM8S207)
\res MCU: STM8L051

\ define the UART buffer length
8 CONSTANT RBLEN

\ then load the controller independent code
#require INTRX

\ put it to work

andrewsclapp

\res MCU: STM8L051
\res export CLK_PCKENR2
5 CONSTANT PCKEN25
#require ]B!
#require WIPE
NVM
: adcCLKCFG ( -- )
  [ 1 CLK_PCKENR2 PCKEN25 ]B!
;
RAM

andrewsclapp

unsigned int ADC_Read (uint16_t Channel) {
    uint16_t ADC_value = 0;

    CLK_PeripheralClockConfig(CLK_Peripheral_ADC1, ENABLE);

    ADC_Init(ADC1, ADC_ConversionMode_Single, ADC_Resolution_12Bit, ADC_Prescaler_1);

    ADC_SamplingTimeConfig(ADC1, ADC_Group_SlowChannels, ADC_SamplingTime_384Cycles);

    ADC_Cmd(ADC1, ENABLE);

andrewsclapp

#require lib/]B!
#require lib/]C!

NVM

\res MCU: STM8L051
\res export PA_ODR PA_DDR PB_ODR PB_DDR PC_ODR PC_DDR PD_ODR PD_DDR
\res export PA_CR1 PB_CR1 PC_CR1 PD_CR1 PA_CR2 PB_CR2 PC_CR2 PD_CR2
\res export CLK_PCKENR2
\res export ADC1_CR1 ADC1_CR2 ADC1_SR ADC1_DRH ADC1_DRL