mesa 25.1.1 Windows XP patch

mesa-25.1.1-WinXP.diff

diff -Nur mesa-25.1.1/src/c11/impl/threads_win32.c mesa-25.1.1-XP/src/c11/impl/threads_win32.c
--- mesa-25.1.1/src/c11/impl/threads_win32.c	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/c11/impl/threads_win32.c	2025-05-26 20:00:09.541552500 +0200
@@ -2,118 +2,47 @@
  * SPDX-License-Identifier: BSL-1.0
  * Copyright yohhoy 2012.
  */
+#define HAVE_PTHREAD 1
+
+#include <stdlib.h>
 #include <assert.h>
 #include <limits.h>
 #include <errno.h>
-#include <process.h>  // MSVCRT
-#include <stdlib.h>
-#include <stdbool.h>
+#include <unistd.h>
+#include <sched.h>
+#include <stdint.h> /* for intptr_t */
 
 #include "c11/threads.h"
 
-#include "threads_win32.h"
-
-#include <windows.h>
-
 /*
 Configuration macro:
-  EMULATED_THREADS_TSS_DTOR_SLOTNUM
-    Max registerable TSS dtor number.
-*/
-
-#define EMULATED_THREADS_TSS_DTOR_SLOTNUM 64  // see TLS_MINIMUM_AVAILABLE
 
+  EMULATED_THREADS_USE_NATIVE_TIMEDLOCK
+    Use pthread_mutex_timedlock() for `mtx_timedlock()'
+    Otherwise use mtx_trylock() + *busy loop* emulation.
+*/
+#if !defined(__CYGWIN__) && !defined(__APPLE__) && !defined(__NetBSD__)
+#define EMULATED_THREADS_USE_NATIVE_TIMEDLOCK
+#endif
 
-static_assert(sizeof(cnd_t) == sizeof(CONDITION_VARIABLE), "The size of cnd_t must equal to CONDITION_VARIABLE");
-static_assert(sizeof(thrd_t) == sizeof(HANDLE), "The size of thrd_t must equal to HANDLE");
-static_assert(sizeof(tss_t) == sizeof(DWORD), "The size of tss_t must equal to DWORD");
-static_assert(sizeof(mtx_t) == sizeof(CRITICAL_SECTION), "The size of mtx_t must equal to CRITICAL_SECTION");
-static_assert(sizeof(once_flag) == sizeof(INIT_ONCE), "The size of once_flag must equal to INIT_ONCE");
+/*---------------------------- types ----------------------------*/
 
 /*
 Implementation limits:
-  - Emulated `mtx_timelock()' with mtx_trylock() + *busy loop*
+  - Conditionally emulation for "mutex with timeout"
+    (see EMULATED_THREADS_USE_NATIVE_TIMEDLOCK macro)
 */
-
 struct impl_thrd_param {
     thrd_start_t func;
     void *arg;
-    thrd_t thrd;
-};
-
-struct thrd_state {
-    thrd_t thrd;
-    bool handle_need_close;
 };
 
-static thread_local struct thrd_state impl_current_thread = { 0 };
-
-static unsigned __stdcall impl_thrd_routine(void *p)
+static void *
+impl_thrd_routine(void *p)
 {
-    struct impl_thrd_param *pack_p = (struct impl_thrd_param *)p;
-    struct impl_thrd_param pack;
-    int code;
-    impl_current_thread.thrd = pack_p->thrd;
-    impl_current_thread.handle_need_close = false;
-    memcpy(&pack, pack_p, sizeof(struct impl_thrd_param));
+    struct impl_thrd_param pack = *((struct impl_thrd_param *)p);
     free(p);
-    code = pack.func(pack.arg);
-    return (unsigned)code;
-}
-
-static time_t impl_timespec2msec(const struct timespec *ts)
-{
-    return (ts->tv_sec * 1000U) + (ts->tv_nsec / 1000000L);
-}
-
-static DWORD impl_abs2relmsec(const struct timespec *abs_time)
-{
-    const time_t abs_ms = impl_timespec2msec(abs_time);
-    struct timespec now;
-    timespec_get(&now, TIME_UTC);
-    const time_t now_ms = impl_timespec2msec(&now);
-    const DWORD rel_ms = (abs_ms > now_ms) ? (DWORD)(abs_ms - now_ms) : 0;
-    return rel_ms;
-}
-
-struct impl_call_once_param { void (*func)(void); };
-static BOOL CALLBACK impl_call_once_callback(PINIT_ONCE InitOnce, PVOID Parameter, PVOID *Context)
-{
-    struct impl_call_once_param *param = (struct impl_call_once_param*)Parameter;
-    (param->func)();
-    ((void)InitOnce); ((void)Context);  // suppress warning
-    return true;
-}
-
-static struct impl_tss_dtor_entry {
-    tss_t key;
-    tss_dtor_t dtor;
-} impl_tss_dtor_tbl[EMULATED_THREADS_TSS_DTOR_SLOTNUM];
-
-static int impl_tss_dtor_register(tss_t key, tss_dtor_t dtor)
-{
-    int i;
-    for (i = 0; i < EMULATED_THREADS_TSS_DTOR_SLOTNUM; i++) {
-        if (!impl_tss_dtor_tbl[i].dtor)
-            break;
-    }
-    if (i == EMULATED_THREADS_TSS_DTOR_SLOTNUM)
-        return 1;
-    impl_tss_dtor_tbl[i].key = key;
-    impl_tss_dtor_tbl[i].dtor = dtor;
-    return 0;
-}
-
-static void impl_tss_dtor_invoke(void)
-{
-    int i;
-    for (i = 0; i < EMULATED_THREADS_TSS_DTOR_SLOTNUM; i++) {
-        if (impl_tss_dtor_tbl[i].dtor) {
-            void* val = tss_get(impl_tss_dtor_tbl[i].key);
-            if (val)
-                (impl_tss_dtor_tbl[i].dtor)(val);
-        }
-    }
+    return (void*)(intptr_t)pack.func(pack.arg);
 }
 
 
@@ -122,10 +51,7 @@
 void
 call_once(once_flag *flag, void (*func)(void))
 {
-    assert(flag && func);
-    struct impl_call_once_param param;
-    param.func = func;
-    InitOnceExecuteOnce((PINIT_ONCE)flag, impl_call_once_callback, (PVOID)&param, NULL);
+    pthread_once(flag, func);
 }
 
 
@@ -135,17 +61,15 @@
 cnd_broadcast(cnd_t *cond)
 {
     assert(cond != NULL);
-    WakeAllConditionVariable((PCONDITION_VARIABLE)cond);
-    return thrd_success;
+    return (pthread_cond_broadcast(cond) == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.3.2
 void
 cnd_destroy(cnd_t *cond)
 {
-    (void)cond;
-    assert(cond != NULL);
-    // do nothing
+    assert(cond);
+    pthread_cond_destroy(cond);
 }
 
 // 7.25.3.3
@@ -153,8 +77,7 @@
 cnd_init(cnd_t *cond)
 {
     assert(cond != NULL);
-    InitializeConditionVariable((PCONDITION_VARIABLE)cond);
-    return thrd_success;
+    return (pthread_cond_init(cond, NULL) == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.3.4
@@ -162,31 +85,32 @@
 cnd_signal(cnd_t *cond)
 {
     assert(cond != NULL);
-    WakeConditionVariable((PCONDITION_VARIABLE)cond);
-    return thrd_success;
+    return (pthread_cond_signal(cond) == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.3.5
 int
 cnd_timedwait(cnd_t *cond, mtx_t *mtx, const struct timespec *abs_time)
 {
-    assert(cond != NULL);
+    int rt;
+
     assert(mtx != NULL);
+    assert(cond != NULL);
     assert(abs_time != NULL);
-    const DWORD timeout = impl_abs2relmsec(abs_time);
-    if (SleepConditionVariableCS((PCONDITION_VARIABLE)cond, (PCRITICAL_SECTION)mtx, timeout))
-        return thrd_success;
-    return (GetLastError() == ERROR_TIMEOUT) ? thrd_timedout : thrd_error;
+
+    rt = pthread_cond_timedwait(cond, mtx, abs_time);
+    if (rt == ETIMEDOUT)
+        return thrd_timedout;
+    return (rt == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.3.6
 int
 cnd_wait(cnd_t *cond, mtx_t *mtx)
 {
-    assert(cond != NULL);
     assert(mtx != NULL);
-    SleepConditionVariableCS((PCONDITION_VARIABLE)cond, (PCRITICAL_SECTION)mtx, INFINITE);
-    return thrd_success;
+    assert(cond != NULL);
+    return (pthread_cond_wait(cond, mtx) == 0) ? thrd_success : thrd_error;
 }
 
 
@@ -195,20 +119,56 @@
 void
 mtx_destroy(mtx_t *mtx)
 {
-    assert(mtx);
-    DeleteCriticalSection((PCRITICAL_SECTION)mtx);
+    assert(mtx != NULL);
+    pthread_mutex_destroy(mtx);
 }
 
+/*
+ * XXX: Workaround when building with -O0 and without pthreads link.
+ *
+ * In such cases constant folding and dead code elimination won't be
+ * available, thus the compiler will always add the pthread_mutexattr*
+ * functions into the binary. As we try to link, we'll fail as the
+ * symbols are unresolved.
+ *
+ * Ideally we'll enable the optimisations locally, yet that does not
+ * seem to work.
+ *
+ * So the alternative workaround is to annotate the symbols as weak.
+ * Thus the linker will be happy and things don't clash when building
+ * with -O1 or greater.
+ */
+#if defined(HAVE_FUNC_ATTRIBUTE_WEAK) && !defined(__CYGWIN__)
+__attribute__((weak))
+int pthread_mutexattr_init(pthread_mutexattr_t *attr);
+
+__attribute__((weak))
+int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type);
+
+__attribute__((weak))
+int pthread_mutexattr_destroy(pthread_mutexattr_t *attr);
+#endif
+
 // 7.25.4.2
 int
 mtx_init(mtx_t *mtx, int type)
 {
+    pthread_mutexattr_t attr;
     assert(mtx != NULL);
     if (type != mtx_plain && type != mtx_timed
       && type != (mtx_plain|mtx_recursive)
       && type != (mtx_timed|mtx_recursive))
         return thrd_error;
-    InitializeCriticalSection((PCRITICAL_SECTION)mtx);
+
+    if ((type & mtx_recursive) == 0) {
+        pthread_mutex_init(mtx, NULL);
+        return thrd_success;
+    }
+
+    pthread_mutexattr_init(&attr);
+    pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE);
+    pthread_mutex_init(mtx, &attr);
+    pthread_mutexattr_destroy(&attr);
     return thrd_success;
 }
 
@@ -217,8 +177,22 @@
 mtx_lock(mtx_t *mtx)
 {
     assert(mtx != NULL);
-    EnterCriticalSection((PCRITICAL_SECTION)mtx);
-    return thrd_success;
+    return (pthread_mutex_lock(mtx) == 0) ? thrd_success : thrd_error;
+}
+
+static int
+threads_timespec_compare(const struct timespec *a, const struct timespec *b)
+{
+    if (a->tv_sec < b->tv_sec) {
+        return -1;
+    } else if (a->tv_sec > b->tv_sec) {
+        return 1;
+    } else if (a->tv_nsec < b->tv_nsec) {
+        return -1;
+    } else if (a->tv_nsec > b->tv_nsec) {
+        return 1;
+    }
+    return 0;
 }
 
 // 7.25.4.4
@@ -227,13 +201,28 @@
 {
     assert(mtx != NULL);
     assert(ts != NULL);
+
+    {
+#ifdef EMULATED_THREADS_USE_NATIVE_TIMEDLOCK
+    int rt;
+    rt = pthread_mutex_timedlock(mtx, ts);
+    if (rt == 0)
+        return thrd_success;
+    return (rt == ETIMEDOUT) ? thrd_timedout : thrd_error;
+#else
     while (mtx_trylock(mtx) != thrd_success) {
-        if (impl_abs2relmsec(ts) == 0)
+        struct timespec now;
+        if (timespec_get(&now, TIME_UTC) != TIME_UTC) {
+            return thrd_error;
+        }
+        if (threads_timespec_compare(ts, &now) < 0)
             return thrd_timedout;
         // busy loop!
         thrd_yield();
     }
     return thrd_success;
+#endif
+    }
 }
 
 // 7.25.4.5
@@ -241,7 +230,7 @@
 mtx_trylock(mtx_t *mtx)
 {
     assert(mtx != NULL);
-    return TryEnterCriticalSection((PCRITICAL_SECTION)mtx) ? thrd_success : thrd_busy;
+    return (pthread_mutex_trylock(mtx) == 0) ? thrd_success : thrd_busy;
 }
 
 // 7.25.4.6
@@ -249,20 +238,9 @@
 mtx_unlock(mtx_t *mtx)
 {
     assert(mtx != NULL);
-    LeaveCriticalSection((PCRITICAL_SECTION)mtx);
-    return thrd_success;
+    return (pthread_mutex_unlock(mtx) == 0) ? thrd_success : thrd_error;
 }
 
-void
-__threads_win32_tls_callback(void)
-{
-    struct thrd_state *state = &impl_current_thread;
-    impl_tss_dtor_invoke();
-    if (state->handle_need_close) {
-        state->handle_need_close = false;
-        CloseHandle(state->thrd.handle);
-    }
-}
 
 /*------------------- 7.25.5 Thread functions -------------------*/
 // 7.25.5.1
@@ -270,22 +248,15 @@
 thrd_create(thrd_t *thr, thrd_start_t func, void *arg)
 {
     struct impl_thrd_param *pack;
-    uintptr_t handle;
     assert(thr != NULL);
     pack = (struct impl_thrd_param *)malloc(sizeof(struct impl_thrd_param));
     if (!pack) return thrd_nomem;
     pack->func = func;
     pack->arg = arg;
-    handle = _beginthreadex(NULL, 0, impl_thrd_routine, pack, CREATE_SUSPENDED, NULL);
-    if (handle == 0) {
+    if (pthread_create(thr, NULL, impl_thrd_routine, pack) != 0) {
         free(pack);
-        if (errno == EAGAIN || errno == EACCES)
-            return thrd_nomem;
         return thrd_error;
     }
-    thr->handle = (void*)handle;
-    pack->thrd = *thr;
-    ResumeThread((HANDLE)handle);
     return thrd_success;
 }
 
@@ -293,49 +264,21 @@
 thrd_t
 thrd_current(void)
 {
-    /* GetCurrentThread() returns a pseudo-handle, which we need
-     * to pass to DuplicateHandle(). Only the resulting handle can be used
-     * from other threads.
-     *
-     * Note that neither handle can be compared to the one by thread_create.
-     * Only the thread IDs - as returned by GetThreadId() and GetCurrentThreadId()
-     * can be compared directly.
-     *
-     * Other potential solutions would be:
-     * - define thrd_t as a thread Ids, but this would mean we'd need to OpenThread for many operations
-     * - use malloc'ed memory for thrd_t. This would imply using TLS for current thread.
-     *
-     * Neither is particularly nice.
-     *
-     * Life would be much easier if C11 threads had different abstractions for
-     * threads and thread IDs, just like C++11 threads does...
-     */
-    struct thrd_state *state = &impl_current_thread;
-    if (state->thrd.handle == NULL)
-    {
-        if (!DuplicateHandle(GetCurrentProcess(), GetCurrentThread(), GetCurrentProcess(),
-            &(state->thrd.handle), 0, false, DUPLICATE_SAME_ACCESS))
-        {
-            abort();
-        }
-        state->handle_need_close = true;
-    }
-    return state->thrd;
+    return pthread_self();
 }
 
 // 7.25.5.3
 int
 thrd_detach(thrd_t thr)
 {
-    CloseHandle(thr.handle);
-    return thrd_success;
+    return (pthread_detach(thr) == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.5.4
 int
 thrd_equal(thrd_t thr0, thrd_t thr1)
 {
-    return GetThreadId(thr0.handle) == GetThreadId(thr1.handle);
+    return pthread_equal(thr0, thr1);
 }
 
 // 7.25.5.5
@@ -343,28 +286,18 @@
 void
 thrd_exit(int res)
 {
-    _endthreadex((unsigned)res);
+    pthread_exit((void*)(intptr_t)res);
 }
 
 // 7.25.5.6
 int
 thrd_join(thrd_t thr, int *res)
 {
-    DWORD w, code;
-    if (thr.handle == NULL) {
-        return thrd_error;
-    }
-    w = WaitForSingleObject(thr.handle, INFINITE);
-    if (w != WAIT_OBJECT_0)
+    void *code;
+    if (pthread_join(thr, &code) != 0)
         return thrd_error;
-    if (res) {
-        if (!GetExitCodeThread(thr.handle, &code)) {
-            CloseHandle(thr.handle);
-            return thrd_error;
-        }
-        *res = (int)code;
-    }
-    CloseHandle(thr.handle);
+    if (res)
+        *res = (int)(intptr_t)code;
     return thrd_success;
 }
 
@@ -372,18 +305,15 @@
 int
 thrd_sleep(const struct timespec *time_point, struct timespec *remaining)
 {
-    (void)remaining;
-    assert(time_point);
-    assert(!remaining); /* not implemented */
-    Sleep((DWORD)impl_timespec2msec(time_point));
-    return 0;
+    assert(time_point != NULL);
+    return nanosleep(time_point, remaining);
 }
 
 // 7.25.5.8
 void
 thrd_yield(void)
 {
-    SwitchToThread();
+    sched_yield();
 }
 
 
@@ -393,33 +323,26 @@
 tss_create(tss_t *key, tss_dtor_t dtor)
 {
     assert(key != NULL);
-    *key = TlsAlloc();
-    if (dtor) {
-        if (impl_tss_dtor_register(*key, dtor)) {
-            TlsFree(*key);
-            return thrd_error;
-        }
-    }
-    return (*key != 0xFFFFFFFF) ? thrd_success : thrd_error;
+    return (pthread_key_create(key, dtor) == 0) ? thrd_success : thrd_error;
 }
 
 // 7.25.6.2
 void
 tss_delete(tss_t key)
 {
-    TlsFree(key);
+    pthread_key_delete(key);
 }
 
 // 7.25.6.3
 void *
 tss_get(tss_t key)
 {
-    return TlsGetValue(key);
+    return pthread_getspecific(key);
 }
 
 // 7.25.6.4
 int
 tss_set(tss_t key, void *val)
 {
-    return TlsSetValue(key, val) ? thrd_success : thrd_error;
+    return (pthread_setspecific(key, val) == 0) ? thrd_success : thrd_error;
 }
Binary files mesa-25.1.1/src/compiler/__pycache__/builtin_types.cpython-312.pyc and mesa-25.1.1-XP/src/compiler/__pycache__/builtin_types.cpython-312.pyc differ
diff -Nur mesa-25.1.1/src/compiler/isaspec/README.rst mesa-25.1.1-XP/src/compiler/isaspec/README.rst
--- mesa-25.1.1/src/compiler/isaspec/README.rst	2025-05-26 22:22:02.989354200 +0200
+++ mesa-25.1.1-XP/src/compiler/isaspec/README.rst	2025-05-21 09:53:29.207378600 +0200
@@ -0,0 +1,354 @@
+ISASPEC - XML Based ISA Specification
+=====================================
+
+isaspec provides a mechanism to describe an instruction set in XML, and
+generate a disassembler and assembler.  The intention is
+to describe the instruction set more formally than hand-coded assembler
+and disassembler, and better decouple the shader compiler from the
+underlying instruction encoding to simplify dealing with instruction
+encoding differences between generations of GPU.
+
+Benefits of a formal ISA description, compared to hand-coded assemblers
+and disassemblers, include easier detection of new bit combinations that
+were not seen before in previous generations due to more rigorous
+description of bits that are expect to be '0' or '1' or 'x' (dontcare)
+and verification that different encodings don't have conflicting bits
+(i.e. that the specification cannot result in more than one valid
+interpretation of any bit pattern).
+
+The isaspec tool and XML schema are intended to be generic (not specific
+to ir3), although there are currently a couple limitations due to short-
+cuts taken to get things up and running (which are mostly not inherent to
+the XML schema, and should not be too difficult to remove from the py and
+decode/disasm utility):
+
+* Maximum "field" size is 64b
+* Fixed instruction size
+
+Often times, especially when new functionality is added in later gens
+while retaining (or at least mostly retaining) backwards compatibility
+with encodings used in earlier generations, the actual encoding can be
+rather messy to describe.  To support this, isaspec provides many flexible
+mechanism, such as conditional overrides and derived fields.  This not
+only allows for describing an irregular instruction encoding, but also
+allows matching an existing disasm syntax (which might not have been
+design around the idea of disassembly based on a formal ISA description).
+
+Bitsets
+-------
+
+The fundamental concept of matching a bit-pattern to an instruction
+decoding/encoding is the concept of a hierarchical tree of bitsets.
+This is intended to match how the HW decodes instructions, where certain
+bits describe the instruction (and sub-encoding, and so on), and other
+bits describe various operands to the instruction.
+
+Bitsets can also be used recursively as the type of a field described
+in another bitset.
+
+The leaves of the tree of instruction bitsets represent every possible
+instruction.  Deciding which instruction a bitpattern is amounts to:
+
+.. code-block:: c
+
+   m = (val & bitsets[n]->mask) & ~bitsets[n]->dontcare;
+
+   if (m == bitsets[n]->match) {
+      /* we've found the instruction description */
+   }
+
+For example, the starting point to decode an ir3 instruction is a 64b
+bitset:
+
+.. code-block:: xml
+
+   <bitset name="#instruction" size="64">
+   	<doc>
+   		Encoding of an ir3 instruction.  All instructions are 64b.
+   	</doc>
+   </bitset>
+
+In the first level of instruction encoding hierarchy, the high three bits
+group things into instruction "categories":
+
+.. code-block:: xml
+
+   <bitset name="#instruction-cat2" extends="#instruction">
+   	<field name="DST" low="32" high="39" type="#reg-gpr"/>
+   	<field name="REPEAT" low="40" high="41" type="#rptN"/>
+   	<field name="SAT" pos="42" type="bool" display="(sat)"/>
+   	<field name="SS" pos="44" type="bool" display="(ss)"/>
+   	<field name="UL" pos="45" type="bool" display="(ul)"/>
+   	<field name="DST_CONV" pos="46" type="bool">
+   		<doc>
+   			Destination register is opposite precision as source, i.e.
+   			if {FULL} is true then destination is half precision, and
+   			visa versa.
+   		</doc>
+   	</field>
+   	<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
+   	<field name="EI" pos="47" type="bool" display="(ei)"/>
+   	<field name="FULL" pos="52" type="bool">
+   		<doc>Full precision source registers</doc>
+   	</field>
+   	<field name="JP" pos="59" type="bool" display="(jp)"/>
+   	<field name="SY" pos="60" type="bool" display="(sy)"/>
+   	<pattern low="61" high="63">010</pattern>  <!-- cat2 -->
+   	<!--
+   		NOTE, both SRC1_R and SRC2_R are defined at this level because
+   		SRC2_R is still a valid bit for (nopN) (REPEAT==0) for cat2
+   		instructions with only a single src
+   	 -->
+   	<field name="SRC1_R" pos="43" type="bool" display="(r)"/>
+   	<field name="SRC2_R" pos="51" type="bool" display="(r)"/>
+   	<derived name="ZERO" expr="#zero" type="bool" display=""/>
+   </bitset>
+
+The ``<pattern>`` elements are the part(s) that determine which leaf-node
+bitset matches against a given bit pattern.  The leaf node's match/mask/
+dontcare bitmasks are a combination of those defined at the leaf node and
+recursively each parent bitclass.
+
+For example, cat2 instructions (ALU instructions with up to two src
+registers) can have either one or two source registers:
+
+.. code-block:: xml
+
+   <bitset name="#instruction-cat2-1src" extends="#instruction-cat2">
+   	<override expr="#cat2-cat3-nop-encoding">
+   		<display>
+   			{SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}
+   		</display>
+   		<derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
+   		<field name="SRC1" low="0" high="15" type="#multisrc">
+   			<param name="ZERO" as="SRC_R"/>
+   			<param name="FULL"/>
+   		</field>
+   	</override>
+   	<display>
+   		{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}
+   	</display>
+   	<pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern>
+   	<pattern low="48" high="50">xxx</pattern>  <!-- COND -->
+   	<field name="SRC1" low="0" high="15" type="#multisrc">
+   		<param name="SRC1_R" as="SRC_R"/>
+   		<param name="FULL"/>
+   	</field>
+   </bitset>
+   
+   <bitset name="absneg.f" extends="#instruction-cat2-1src">
+   	<pattern low="53" high="58">000110</pattern>
+   </bitset>
+
+In this example, ``absneg.f`` is a concrete cat2 instruction (leaf node of
+the bitset inheritance tree) which has a single src register.  At the
+``#instruction-cat2-1src`` level, bits that are used for the 2nd src arg
+and condition code (for cat2 instructions which use a condition code) are
+defined as 'x' (dontcare), which matches our understanding of the hardware
+(but also lets the disassembler flag cases where '1' bits show up in places
+we don't expect, which may signal a new instruction (sub)encoding).
+
+You'll notice that ``SRC1`` refers back to a different bitset hierarchy
+that describes various different src register encoding (used for cat2 and
+cat4 instructions), i.e. GPR vs CONST vs relative GPR/CONST.  For fields
+which have bitset types, parameters can be "passed" in via ``<param>``
+elements, which can be referred to by the display template string, and/or
+expressions.  For example, this helps to deal with cases where other fields
+outside of that bitset control the encoding/decoding, such as in the
+``#multisrc`` example:
+
+.. code-block:: xml
+
+   <bitset name="#multisrc" size="16">
+   	<doc>
+   		Encoding for instruction source which can be GPR/CONST/IMMED
+   		or relative GPR/CONST.
+   	</doc>
+   </bitset>
+
+   ...
+
+   <bitset name="#multisrc-gpr" extends="#multisrc">
+   	<display>
+   		{ABSNEG}{SRC_R}{HALF}{SRC}
+   	</display>
+   	<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
+   	<field name="SRC" low="0" high="7" type="#reg-gpr"/>
+   	<pattern low="8" high="13">000000</pattern>
+   	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
+   </bitset>
+
+At some level in the bitset inheritance hierarchy, there is expected to be a
+``<display>`` element specifying a template string used during bitset
+decoding.  The display template consists of references to fields (which may
+be derived fields) specified as ``{FIELDNAME}`` and other characters
+which are just echoed through to the resulting decoded bitset.
+
+The special field reference ``{NAME}`` prints the name of the bitset. This is
+often useful when the ``<display>`` element is at a higher level than the
+leaves of the hierarchy, for example a whole class of similar instructions that
+only differ in opcode.
+
+Sometimes there may be multiple variants of an instruction that must be
+different bitsets, for example because they are so different that they must
+derive from different bitsets, but they have the same name. Because bitset
+names must be unique in the encoder, this can be a problem, but this can worked
+around with the ``displayname`` attribute on the ``bitset`` which changes how
+``{NAME}`` is displayed but not the name used in the encoder. ``displayname``
+is only useful for leaf bitsets.
+
+It is possible to define a line column alignment value per field to influence
+the visual output. It needs to be specified as ``{FIELDNAME:align=xx}``.
+
+The ``<override>`` element will be described in the next section, but it
+provides for both different decoded instruction syntax/mnemonics (when
+simply providing a different display template string) as well as instruction
+encoding where different ranges of bits have a different meaning based on
+some other bitfield (or combination of bitfields).  In this example it is
+used to cover the cases where ``SRCn_R`` has a different meaning and a
+different disassembly syntax depending on whether ``REPEAT`` equals zero.
+
+The ``<template>`` element can be used to represent a placeholder for a more
+complex ``<display>`` substring.
+
+Overrides
+---------
+
+In many cases, a bitset is not convenient for describing the expected
+disasm syntax, and/or interpretation of some range of bits differs based
+on some other field or combination of fields.  These *could* be modeled
+as different derived bitsets, at the expense of a combinatorial explosion
+of the size of the bitset inheritance tree.  For example, *every* cat2
+(and cat3) instruction has both a ``(nopN)`` interpretation in addition to
+the ``(rptN`)`` interpretation.
+
+An ``<override>`` in a bitset allows to redefine the display string, and/or
+field definitions from the default case.  If the override's expr(ession)
+evaluates to non-zero, ``<display>``, ``<field>``, and ``<derived>``
+elements take precedence over what is defined in the top-level of the
+bitset (i.e. the default case).
+
+Expressions
+-----------
+
+Both ``<override>`` and ``<derived>`` fields make use of ``<expr>`` elements,
+either defined inline, or defined and named at the top level and referred to
+by name in multiple other places.  An expression is a simple 'C' expression
+which can reference fields (including other derived fields) with the same
+``{FIELDNAME}`` syntax as display template strings.  For example:
+
+.. code-block:: xml
+
+   <expr name="#cat2-cat3-nop-encoding">
+   	(({SRC1_R} != 0) || ({SRC2_R} != 0)) &amp;&amp; ({REPEAT} == 0)
+   </expr>
+
+In the case of ``<override>`` elements, the override applies if the expression
+evaluates to non-zero.  In the case of ``<derived>`` fields, the expression
+evaluates to the value of the derived field.
+
+Branching
+---------
+
+isaspec supports a few special field types for printing branch destinations. If
+``isaspec_decode_options::branch_labels`` is true, a pre-pass over the program
+to be disassembled determines which instructions are branch destinations and
+then they are printed when disassembling, in addition to printing the name of
+the destination when printing the field itself.
+
+There are two different types, which affect how the destination is computed. If
+the field type is ``branch``, then the field is interpreted as a signed offset
+from the current instruction. If the type is ``absbranch``, then it is
+interpreted as an offset from the first instruction to be disassembled. In
+either case, the offset is multiplied by the instruction size.
+
+For example, here is what a signed-offset unconditional jump instruction might
+look like:
+
+.. code-block:: xml
+
+   <bitset name="jump" extends="#instruction">
+      <display>
+         jump #{OFFSET}
+      </display>
+      <pattern low="26" high="31">110010</pattern> <!-- opcode goes here -->
+      <field name="OFFSET" low="0" high="25" type="branch"/>
+   </bitset>
+
+This would produce a disassembly like ``jump #l42`` if the destination is 42
+instructions after the start of the disassembly. The destination would be
+preceded by a line with just ``l42:``.
+
+``branch`` and ``absbranch`` fields can additionally have a ``call="true"``
+attribute. For now, this just changes the disassembly. In particular the label
+prefix is changed to ``fxn`` and an extra empty line before the destination is
+added to visually separate the disassembly into functions. So, for example, a
+call instruction defined like this:
+
+.. code-block:: xml
+
+   <bitset name="call" extends="#instruction">
+      <display>
+         call #{OFFSET}
+      </display>
+      <pattern low="26" high="31">110010</pattern> <!-- opcode goes here -->
+      <field name="OFFSET" low="0" high="25" type="branch" call="true"/>
+   </bitset>
+
+will disassemble to ``call #fxn42``.
+
+Finally, users with special knowledge about where execution may start can define
+"entrypoints" when disassembling which are printed like function call
+destinations, with an extra empty line, but with an arbitrary user-defined
+name. Names that are ``fxn`` or ``l`` followed by a number are discouraged
+because they may clash with automatically-generated names.
+
+Encoding
+--------
+
+To facilitate instruction encoding, ``<encode>`` elements can be provided
+to teach the generated instruction packing code how to map from data structures
+representing the IR to fields.  For example:
+
+.. code-block:: xml
+
+   <bitset name="#instruction" size="64">
+   	<doc>
+   		Encoding of an ir3 instruction.  All instructions are 64b.
+   	</doc>
+   	<gen min="300"/>
+   	<encode type="struct ir3_instruction *" case-prefix="OPC_">
+   		<!--
+   			Define mapping from encode src to individual fields,
+   			which are common across all instruction categories
+   			at the root instruction level
+   
+   			Not all of these apply to all instructions, but we
+   			can define mappings here for anything that is used
+   			in more than one instruction category.  For things
+   			that are specific to a single instruction category,
+   			mappings should be defined at that level instead.
+   		 -->
+   		<map name="DST">src->regs[0]</map>
+   		<map name="SRC1">src->regs[1]</map>
+   		<map name="SRC2">src->regs[2]</map>
+   		<map name="SRC3">src->regs[3]</map>
+   		<map name="REPEAT">src->repeat</map>
+   		<map name="SS">!!(src->flags &amp; IR3_INSTR_SS)</map>
+   		<map name="JP">!!(src->flags &amp; IR3_INSTR_JP)</map>
+   		<map name="SY">!!(src->flags &amp; IR3_INSTR_SY)</map>
+   		<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
+   		<map name="EQ">0</map>  <!-- We don't use this (yet) -->
+   		<map name="SAT">!!(src->flags &amp; IR3_INSTR_SAT)</map>
+   	</encode>
+   </bitset>
+
+The ``type`` attribute specifies that the input to encoding an instruction
+is a ``struct ir3_instruction *``.  In the case of bitset hierarchies with
+multiple possible leaf nodes, a ``case-prefix`` attribute should be supplied
+along with a function that maps the bitset encode source to an enum value
+with the specified prefix prepended to uppercased leaf node name.  I.e. in
+this case, "add.f" becomes ``OPC_ADD_F``.
+
+Individual ``<map>`` elements teach the encoder how to map from the encode
+source to fields in the encoded instruction.
Binary files mesa-25.1.1/src/compiler/nir/__pycache__/nir_algebraic.cpython-312.pyc and mesa-25.1.1-XP/src/compiler/nir/__pycache__/nir_algebraic.cpython-312.pyc differ
Binary files mesa-25.1.1/src/compiler/nir/__pycache__/nir_intrinsics.cpython-312.pyc and mesa-25.1.1-XP/src/compiler/nir/__pycache__/nir_intrinsics.cpython-312.pyc differ
Binary files mesa-25.1.1/src/compiler/nir/__pycache__/nir_opcodes.cpython-312.pyc and mesa-25.1.1-XP/src/compiler/nir/__pycache__/nir_opcodes.cpython-312.pyc differ
diff -Nur mesa-25.1.1/src/gallium/drivers/asahi/.clang-format mesa-25.1.1-XP/src/gallium/drivers/asahi/.clang-format
--- mesa-25.1.1/src/gallium/drivers/asahi/.clang-format	2025-05-26 22:22:04.749814200 +0200
+++ mesa-25.1.1-XP/src/gallium/drivers/asahi/.clang-format	2025-05-21 09:53:29.448177000 +0200
@@ -0,0 +1,8 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: true
+ColumnLimit: 80
+BreakStringLiterals: false
+SpaceBeforeParens: ControlStatementsExceptControlMacros
diff -Nur mesa-25.1.1/src/gallium/drivers/freedreno/.clang-format mesa-25.1.1-XP/src/gallium/drivers/freedreno/.clang-format
--- mesa-25.1.1/src/gallium/drivers/freedreno/.clang-format	2025-05-26 22:22:05.077821500 +0200
+++ mesa-25.1.1-XP/src/gallium/drivers/freedreno/.clang-format	2025-05-21 09:53:29.466686200 +0200
@@ -0,0 +1,58 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: true
+ColumnLimit: 80
+BreakStringLiterals: false
+
+ForEachMacros:
+  - ir2_foreach_instr
+  - ir2_foreach_live_reg
+  - ir2_foreach_avail
+  - ir2_foreach_src
+  - foreach_batch
+  - perf_time
+  - perf_time_ctx
+  - foreach_sched_node
+  - foreach_src
+  - foreach_src_n
+  - foreach_src_if
+  - foreach_src_with_alias_n
+  - foreach_src_in_alias_group_n
+  - foreach_src_in_alias_group
+  - foreach_dst
+  - foreach_dst_n
+  - foreach_dst_if
+  - ra_foreach_dst
+  - ra_foreach_src
+  - ra_foreach_src_rev
+  - foreach_ssa_use
+  - foreach_ssa_srcp_n
+  - foreach_ssa_srcp
+  - foreach_ssa_src_n
+  - foreach_ssa_src
+  - foreach_input_n
+  - foreach_input
+  - foreach_instr
+  - foreach_instr_rev
+  - foreach_instr_safe
+  - foreach_instr_from
+  - foreach_instr_from_safe
+  - foreach_block
+  - foreach_block_safe
+  - foreach_block_rev
+  - foreach_array
+  - foreach_array_safe
+  - foreach_interval
+  - foreach_interval_safe
+  - foreach_interval_rev
+  - foreach_interval_rev_safe
+  - foreach_line_in_section
+  - foreach_submit
+  - foreach_submit_safe
+  - foreach_instr_rpt
+  - foreach_instr_rpt_excl
+  - foreach_instr_rpt_excl_safe
+  - foreach_bo
+  - foreach_bo_safe
diff -Nur mesa-25.1.1/src/gallium/drivers/panfrost/.clang-format mesa-25.1.1-XP/src/gallium/drivers/panfrost/.clang-format
--- mesa-25.1.1/src/gallium/drivers/panfrost/.clang-format	2025-05-26 22:22:05.959041100 +0200
+++ mesa-25.1.1-XP/src/gallium/drivers/panfrost/.clang-format	2025-05-21 09:53:29.538602000 +0200
@@ -0,0 +1,84 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: true
+ColumnLimit: 80
+BreakStringLiterals: false
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+ForEachMacros: [
+  'BITSET_FOREACH_SET',
+  'bi_foreach_block',
+  'bi_foreach_block_from',
+  'bi_foreach_block_from_rev',
+  'bi_foreach_block_rev',
+  'bi_foreach_clause_in_block',
+  'bi_foreach_clause_in_block_from',
+  'bi_foreach_clause_in_block_from_rev',
+  'bi_foreach_clause_in_block_rev',
+  'bi_foreach_clause_in_block_safe',
+  'bi_foreach_dest',
+  'bi_foreach_instr_and_src_in_tuple',
+  'bi_foreach_instr_global',
+  'bi_foreach_instr_global_rev',
+  'bi_foreach_instr_global_rev_safe',
+  'bi_foreach_instr_global_safe',
+  'bi_foreach_instr_in_block',
+  'bi_foreach_instr_in_block_from',
+  'bi_foreach_instr_in_block_from_rev',
+  'bi_foreach_instr_in_block_rev',
+  'bi_foreach_instr_in_block_safe',
+  'bi_foreach_instr_in_block_safe_rev',
+  'bi_foreach_instr_in_clause',
+  'bi_foreach_instr_in_clause_rev',
+  'bi_foreach_instr_in_tuple',
+  'bi_foreach_predecessor',
+  'bi_foreach_src',
+  'bi_foreach_ssa_dest',
+  'bi_foreach_ssa_src',
+  'bi_foreach_successor',
+  'cs_case',
+  'cs_default',
+  'cs_else',
+  'cs_emit',
+  'cs_exception_handler_def',
+  'cs_if',
+  'cs_match',
+  'cs_update_compute_ctx',
+  'cs_update_frag_ctx',
+  'cs_update_progress_seqno',
+  'cs_update_vt_ctx',
+  'cs_while',
+  'foreach_batch',
+  'list_for_each_entry_safe',
+  'mir_foreach_block',
+  'mir_foreach_block_from',
+  'mir_foreach_bundle_in_block',
+  'mir_foreach_bundle_in_block_rev',
+  'mir_foreach_instr_global',
+  'mir_foreach_instr_global_safe',
+  'mir_foreach_instr_in_block',
+  'mir_foreach_instr_in_block_from',
+  'mir_foreach_instr_in_block_from_rev',
+  'mir_foreach_instr_in_block_rev',
+  'mir_foreach_instr_in_block_safe',
+  'mir_foreach_instr_in_block_safe_rev',
+  'mir_foreach_instr_in_block_scheduled_rev',
+  'mir_foreach_predecessor',
+  'mir_foreach_src',
+  'nir_foreach_variable_with_modes',
+  'nir_foreach_shader_in_variable',
+  'nodearray_dense_foreach',
+  'nodearray_dense_foreach_64',
+  'nodearray_sparse_foreach',
+  'pan_cast_and_pack',
+  'pan_cast_and_pack_nodefaults',
+  'pan_foreach_instr_in_block_rev',
+  'pan_foreach_predecessor',
+  'pan_foreach_successor',
+  'pan_pack',
+  'pan_pack_nodefaults',
+  'pan_section_pack',
+  'panvk_cs_reg_upd_ctx',
+  'u_foreach_bit',
+]
Binary files mesa-25.1.1/src/gallium/drivers/zink/__pycache__/zink_extensions.cpython-312.pyc and mesa-25.1.1-XP/src/gallium/drivers/zink/__pycache__/zink_extensions.cpython-312.pyc differ
diff -Nur mesa-25.1.1/src/gallium/winsys/asahi/drm/.clang-format mesa-25.1.1-XP/src/gallium/winsys/asahi/drm/.clang-format
--- mesa-25.1.1/src/gallium/winsys/asahi/drm/.clang-format	2025-05-26 22:22:08.287901800 +0200
+++ mesa-25.1.1-XP/src/gallium/winsys/asahi/drm/.clang-format	2025-05-21 09:53:29.797865000 +0200
@@ -0,0 +1,8 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: true
+ColumnLimit: 80
+BreakStringLiterals: false
+SpaceBeforeParens: ControlStatementsExceptControlMacros
diff -Nur mesa-25.1.1/src/gallium/winsys/panfrost/drm/.clang-format mesa-25.1.1-XP/src/gallium/winsys/panfrost/drm/.clang-format
--- mesa-25.1.1/src/gallium/winsys/panfrost/drm/.clang-format	2025-05-26 22:22:08.379173400 +0200
+++ mesa-25.1.1-XP/src/gallium/winsys/panfrost/drm/.clang-format	2025-05-21 09:53:29.801869000 +0200
@@ -0,0 +1,84 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: true
+ColumnLimit: 80
+BreakStringLiterals: false
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+ForEachMacros: [
+  'BITSET_FOREACH_SET',
+  'bi_foreach_block',
+  'bi_foreach_block_from',
+  'bi_foreach_block_from_rev',
+  'bi_foreach_block_rev',
+  'bi_foreach_clause_in_block',
+  'bi_foreach_clause_in_block_from',
+  'bi_foreach_clause_in_block_from_rev',
+  'bi_foreach_clause_in_block_rev',
+  'bi_foreach_clause_in_block_safe',
+  'bi_foreach_dest',
+  'bi_foreach_instr_and_src_in_tuple',
+  'bi_foreach_instr_global',
+  'bi_foreach_instr_global_rev',
+  'bi_foreach_instr_global_rev_safe',
+  'bi_foreach_instr_global_safe',
+  'bi_foreach_instr_in_block',
+  'bi_foreach_instr_in_block_from',
+  'bi_foreach_instr_in_block_from_rev',
+  'bi_foreach_instr_in_block_rev',
+  'bi_foreach_instr_in_block_safe',
+  'bi_foreach_instr_in_block_safe_rev',
+  'bi_foreach_instr_in_clause',
+  'bi_foreach_instr_in_clause_rev',
+  'bi_foreach_instr_in_tuple',
+  'bi_foreach_predecessor',
+  'bi_foreach_src',
+  'bi_foreach_ssa_dest',
+  'bi_foreach_ssa_src',
+  'bi_foreach_successor',
+  'cs_case',
+  'cs_default',
+  'cs_else',
+  'cs_emit',
+  'cs_exception_handler_def',
+  'cs_if',
+  'cs_match',
+  'cs_update_compute_ctx',
+  'cs_update_frag_ctx',
+  'cs_update_progress_seqno',
+  'cs_update_vt_ctx',
+  'cs_while',
+  'foreach_batch',
+  'list_for_each_entry_safe',
+  'mir_foreach_block',
+  'mir_foreach_block_from',
+  'mir_foreach_bundle_in_block',
+  'mir_foreach_bundle_in_block_rev',
+  'mir_foreach_instr_global',
+  'mir_foreach_instr_global_safe',
+  'mir_foreach_instr_in_block',
+  'mir_foreach_instr_in_block_from',
+  'mir_foreach_instr_in_block_from_rev',
+  'mir_foreach_instr_in_block_rev',
+  'mir_foreach_instr_in_block_safe',
+  'mir_foreach_instr_in_block_safe_rev',
+  'mir_foreach_instr_in_block_scheduled_rev',
+  'mir_foreach_predecessor',
+  'mir_foreach_src',
+  'nir_foreach_variable_with_modes',
+  'nir_foreach_shader_in_variable',
+  'nodearray_dense_foreach',
+  'nodearray_dense_foreach_64',
+  'nodearray_sparse_foreach',
+  'pan_cast_and_pack',
+  'pan_cast_and_pack_nodefaults',
+  'pan_foreach_instr_in_block_rev',
+  'pan_foreach_predecessor',
+  'pan_foreach_successor',
+  'pan_pack',
+  'pan_pack_nodefaults',
+  'pan_section_pack',
+  'panvk_cs_reg_upd_ctx',
+  'u_foreach_bit',
+]
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/apiexec.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/apiexec.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/glX_XML.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/glX_XML.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/gl_XML.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/gl_XML.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/license.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/license.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/marshal_XML.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/marshal_XML.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/static_data.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/static_data.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/glapi/gen/__pycache__/typeexpr.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/glapi/gen/__pycache__/typeexpr.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mapi/new/__pycache__/genCommon.cpython-312.pyc and mesa-25.1.1-XP/src/mapi/new/__pycache__/genCommon.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mesa/main/__pycache__/format_parser.cpython-312.pyc and mesa-25.1.1-XP/src/mesa/main/__pycache__/format_parser.cpython-312.pyc differ
Binary files mesa-25.1.1/src/mesa/main/__pycache__/get_hash_params.cpython-312.pyc and mesa-25.1.1-XP/src/mesa/main/__pycache__/get_hash_params.cpython-312.pyc differ
diff -Nur mesa-25.1.1/src/util/cnd_monotonic.c mesa-25.1.1-XP/src/util/cnd_monotonic.c
--- mesa-25.1.1/src/util/cnd_monotonic.c	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/util/cnd_monotonic.c	2025-05-26 20:05:19.993031200 +0200
@@ -25,39 +25,25 @@
  *
  **************************************************************************/
 
+#define HAVE_PTHREAD 1
+
 #include "cnd_monotonic.h"
 #include "util/os_time.h"
 #include "util/timespec.h"
 
 #include <assert.h>
 
-#ifdef _WIN32
-#include <windows.h>
-
-static_assert(sizeof(struct u_cnd_monotonic) == sizeof(CONDITION_VARIABLE),
-              "The size of u_cnd_monotonic must equal to CONDITION_VARIABLE");
-static_assert(sizeof(mtx_t) == sizeof(CRITICAL_SECTION),
-              "The size of mtx_t must equal to CRITICAL_SECTION");
-#endif
-
 int
 u_cnd_monotonic_init(struct u_cnd_monotonic *cond)
 {
    assert(cond != NULL);
 
-#ifdef _WIN32
-   InitializeConditionVariable((PCONDITION_VARIABLE)cond);
-   return thrd_success;
-#else
    int ret = thrd_error;
    pthread_condattr_t condattr;
    if (pthread_condattr_init(&condattr) == 0) {
       if (
          // pthread_condattr_setclock is not supported on Apple platforms.
          // Instead, they use a relative deadline. See u_cnd_monotonic_timedwait.
-#ifndef __APPLE__
-         (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC) == 0) &&
-#endif
          (pthread_cond_init(&cond->cond, &condattr) == 0)) {
          ret = thrd_success;
       }
@@ -66,7 +52,6 @@
    }
 
    return ret;
-#endif
 }
 
 void
@@ -74,11 +59,7 @@
 {
    assert(cond != NULL);
 
-#ifdef _WIN32
-   // Do nothing
-#else
    pthread_cond_destroy(&cond->cond);
-#endif
 }
 
 int
@@ -86,12 +67,7 @@
 {
    assert(cond != NULL);
 
-#ifdef _WIN32
-   WakeAllConditionVariable((PCONDITION_VARIABLE)cond);
-   return thrd_success;
-#else
    return (pthread_cond_broadcast(&cond->cond) == 0) ? thrd_success : thrd_error;
-#endif
 }
 
 int
@@ -99,12 +75,7 @@
 {
    assert(cond != NULL);
 
-#ifdef _WIN32
-   WakeConditionVariable((PCONDITION_VARIABLE)cond);
-   return thrd_success;
-#else
    return (pthread_cond_signal(&cond->cond) == 0) ? thrd_success : thrd_error;
-#endif
 }
 
 int
@@ -115,29 +86,10 @@
    assert(mtx != NULL);
    assert(abs_time != NULL);
 
-#ifdef _WIN32
-   const uint64_t future = (abs_time->tv_sec * 1000) + (abs_time->tv_nsec / 1000000);
-   const uint64_t now = os_time_get_nano() / 1000000;
-   const DWORD timeout = (future > now) ? (DWORD)(future - now) : 0;
-   if (SleepConditionVariableCS((PCONDITION_VARIABLE)cond,
-                                (PCRITICAL_SECTION)mtx, timeout))
-      return thrd_success;
-   return (GetLastError() == ERROR_TIMEOUT) ? thrd_timedout : thrd_error;
-#else
-#ifdef __APPLE__
-   // Convert to a relative wait as we can't use CLOCK_MONOTONIC deadlines on macOS.
-   struct timespec now_time;
-   timespec_get(&now_time, TIME_MONOTONIC);
-   struct timespec rel_time;
-   timespec_sub_saturate(&rel_time, abs_time, &now_time);
-   int rt = pthread_cond_timedwait_relative_np(&cond->cond, mtx, &rel_time);
-#else
    int rt = pthread_cond_timedwait(&cond->cond, mtx, abs_time);
-#endif
    if (rt == ETIMEDOUT)
       return thrd_timedout;
    return (rt == 0) ? thrd_success : thrd_error;
-#endif
 }
 
 int
@@ -146,11 +98,5 @@
    assert(cond != NULL);
    assert(mtx != NULL);
 
-#ifdef _WIN32
-   SleepConditionVariableCS((PCONDITION_VARIABLE)cond,
-                            (PCRITICAL_SECTION)mtx, INFINITE);
-   return thrd_success;
-#else
    return (pthread_cond_wait(&cond->cond, mtx) == 0) ? thrd_success : thrd_error;
-#endif
 }
diff -Nur mesa-25.1.1/src/util/cnd_monotonic.h mesa-25.1.1-XP/src/util/cnd_monotonic.h
--- mesa-25.1.1/src/util/cnd_monotonic.h	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/util/cnd_monotonic.h	2025-05-26 20:07:16.051983900 +0200
@@ -28,6 +28,9 @@
 #ifndef CND_MONOTONIC_H
 #define CND_MONOTONIC_H
 
+#define HAVE_PTHREAD 1
+#include <pthread.h>
+
 #include "c11/threads.h"
 
 #include "util/os_time.h"
@@ -40,11 +43,7 @@
 
 struct u_cnd_monotonic
 {
-#ifdef _WIN32
-   void *Ptr;
-#else
    pthread_cond_t cond;
-#endif
 };
 
 int u_cnd_monotonic_init(struct u_cnd_monotonic *cond);
Binary files mesa-25.1.1/src/util/format/__pycache__/u_format_pack.cpython-312.pyc and mesa-25.1.1-XP/src/util/format/__pycache__/u_format_pack.cpython-312.pyc differ
Binary files mesa-25.1.1/src/util/format/__pycache__/u_format_parse.cpython-312.pyc and mesa-25.1.1-XP/src/util/format/__pycache__/u_format_parse.cpython-312.pyc differ
Binary files mesa-25.1.1/src/util/perf/__pycache__/u_trace.cpython-312.pyc and mesa-25.1.1-XP/src/util/perf/__pycache__/u_trace.cpython-312.pyc differ
diff -Nur mesa-25.1.1/src/util/rwlock.c mesa-25.1.1-XP/src/util/rwlock.c
--- mesa-25.1.1/src/util/rwlock.c	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/util/rwlock.c	2025-05-26 18:08:29.274718200 +0200
@@ -5,69 +5,35 @@
  */
 
 #include <assert.h>
+#define HAVE_PTHREAD 1
 #include "rwlock.h"
 
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-#include <windows.h>
-static_assert(sizeof(struct u_rwlock) == sizeof(SRWLOCK),
-   "struct u_rwlock should have equal size with SRWLOCK");
-#endif
-
 int u_rwlock_init(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   InitializeSRWLock((PSRWLOCK)(&rwlock->rwlock));
-   return 0;
-#else
    return pthread_rwlock_init(&rwlock->rwlock, NULL);
-#endif
 }
 
 int u_rwlock_destroy(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   return 0;
-#else
    return pthread_rwlock_destroy(&rwlock->rwlock);
-#endif
 }
 
 int u_rwlock_rdlock(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   AcquireSRWLockShared((PSRWLOCK)&rwlock->rwlock);
-   return 0;
-#else
    return pthread_rwlock_rdlock(&rwlock->rwlock);
-#endif
 }
 
 int u_rwlock_rdunlock(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   ReleaseSRWLockShared((PSRWLOCK)&rwlock->rwlock);
-   return 0;
-#else
    return pthread_rwlock_unlock(&rwlock->rwlock);
-#endif
 }
 
 int u_rwlock_wrlock(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   AcquireSRWLockExclusive((PSRWLOCK)&rwlock->rwlock);
-   return 0;
-#else
    return pthread_rwlock_wrlock(&rwlock->rwlock);
-#endif
 }
 
 int u_rwlock_wrunlock(struct u_rwlock *rwlock)
 {
-#if defined(_WIN32) && !defined(HAVE_PTHREAD)
-   ReleaseSRWLockExclusive((PSRWLOCK)&rwlock->rwlock);
-   return 0;
-#else
    return pthread_rwlock_unlock(&rwlock->rwlock);
-#endif
 }
diff -Nur mesa-25.1.1/src/util/u_qsort.cpp mesa-25.1.1-XP/src/util/u_qsort.cpp
--- mesa-25.1.1/src/util/u_qsort.cpp	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/util/u_qsort.cpp	2025-05-26 15:42:45.263641600 +0200
@@ -21,6 +21,7 @@
  * IN THE SOFTWARE.
  */
 
+#include <cstdlib>
 #include "u_qsort.h"
 #include <thread>
 
diff -Nur mesa-25.1.1/src/util/u_thread.c mesa-25.1.1-XP/src/util/u_thread.c
--- mesa-25.1.1/src/util/u_thread.c	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/src/util/u_thread.c	2025-05-26 18:13:08.876805700 +0200
@@ -37,15 +37,7 @@
 int
 util_get_current_cpu(void)
 {
-#if DETECT_OS_LINUX && !DETECT_OS_ANDROID
-   return sched_getcpu();
-
-#elif defined(_WIN32) && !defined(HAVE_PTHREAD)
-   return GetCurrentProcessorNumber();
-
-#else
    return -1;
-#endif
 }
 
 int u_thread_create(thrd_t *thrd, int (*routine)(void *), void *param)
Binary files mesa-25.1.1/src/vulkan/util/__pycache__/vk_entrypoints.cpython-312.pyc and mesa-25.1.1-XP/src/vulkan/util/__pycache__/vk_entrypoints.cpython-312.pyc differ
Binary files mesa-25.1.1/src/vulkan/util/__pycache__/vk_extensions.cpython-312.pyc and mesa-25.1.1-XP/src/vulkan/util/__pycache__/vk_extensions.cpython-312.pyc differ
--- mesa-25.1.1/meson.build	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/meson.build	2025-05-27 08:01:59.049241100 +0200
@@ -1025,7 +1025,7 @@
   pre_args += '-D__EXTENSIONS__'
 elif host_machine.system() == 'windows'
   pre_args += [
-    '-D_WINDOWS', '-D_WIN32_WINNT=0x0A00', '-DWINVER=0x0A00',
+    '-D_WINDOWS', '-D_WIN32_WINNT=0x0501', '-DWINVER=0x0501',
     '-DPIPE_SUBSYSTEM_WINDOWS_USER',
     '-D_USE_MATH_DEFINES',  # XXX: scons didn't use this for mingw
   ]
@@ -1047,9 +1047,6 @@
     # _UCRT
     if cc.compiles('''
       #include <string.h>
-      #if defined(__MINGW32__) && defined(_UCRT)
-      #error
-      #endif
       int main(void) { return 0; }''')
       pre_args += ['-D__MSVCRT_VERSION__=0x0700']
     endif
@@ -1753,7 +1750,7 @@
 elif with_gallium_clover
   _llvm_version = '>= 11.0.0'
 else
-  _llvm_version = '>= 5.0.0'
+  _llvm_version = '>= 5.0.0'
 endif
 
 _shared_llvm = get_option('shared-llvm') \
--- mesa-25.1.1/meson.options	2025-05-21 09:15:28.000000000 +0200
+++ mesa-25.1.1-XP/meson.options	2025-05-26 13:13:49.014673600 +0200
@@ -752,10 +752,10 @@
 option(
   'min-windows-version',
   type : 'integer',
-  min : 7,
+  min : 5,
   max : 11,
-  value : 8,
-  description : 'Minimum Windows version to support. Defaults to Windows 8.'
+  value : 5,
+  description : 'Minimum Windows version to support. Defaults to Windows 2000.'
 )
 
 option(