Created
March 20, 2015 10:41
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Simple tavor format to generate RISC-V Assembly instructions
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START = ".global _start" "\n" "_start:" "\n" +(line "\n") | |
/*register_zero = "x0"*/ | |
register_name = "x"[0-31] | |
instruction_r_type = inst_r " " register_name "," register_name "," register_name | |
instruction_i_type = (inst_i | inst_l | inst_s) " " register_name "," register_name "," +([\d]) //12 bit immediate | |
instruction_u_type = (inst_u | inst_jal) " " register_name "," +([\d]) //20bit immediate | |
instruction_syscalls = inst_system | ( inst_system_d " " register_name ) | |
/*RV32I and RV32M [register to register instructions]*/ | |
inst_r = "ADD" | "SLT" | "SLTU" | "SUB" | "SLL" | "XOR" | "SRL" | "SRA" | "OR" | "AND" | "MUL" | "MULH" | "MULHSU" | "DIV" | "DIVU" | "REM" | "REMU" | |
//nop = "NOP" | |
/*RV32I [register immediate + control transfer instructions]*/ | |
inst_i = "BEQ" | "BNE" |"BLT" |"BGE" | "BLTU" | "BGEU" |"JALR" | "ADDI" | "SLTI" | "SLTIU" | "ANDI" | "ORI" | "XORI" | "SLLI" | "SRLI" | "SRAI" //Shift Amount take 5 bits | |
inst_l = "LB" | "LH" | "LW" | "LBU" | "LHU" | |
inst_s = "SB" | "SH" | |
/*RV32I [register Immediate instructions u type] */ | |
inst_u = "LUI" | "AUIPC" //20 bit immediate | |
inst_jal = "JAL" //take 20 bit immediate | |
//System Instructions | |
inst_system = "FENCE" | "FENCE.I" | "SCALL" | "SBREAK" | |
inst_system_d = "RDCYCLE" | "RDCYCLEH" | "RDTIME" | "RDTIMEH" | "RDINSTRET" | "RDINSTRETH" | |
line = instruction_r_type | instruction_i_type | instruction_u_type | instruction_syscalls |
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