asahilina

AGX coherency, caching, and TLBs

These are just some notes on my current understanding of the subtleties of the AGX memory model and the TLB/caching issues I'm seeing.

Hypervisor shenanigans

TLBI instructions do not broadcast to the GPU from EL1 with stage 2 translation enabled. That's it. That's what the bug was.

GPU side

asahilina

100 414.0
200 414.0
300 415.0
310 415.0
320 415.0
330 416.0
340 416.0
350 417.0
360 417.0
370 419.0

asahilina

100 16734.0
110 16782.0
120 16833.0
130 16883.0
140 16936.0
150 16991.0
160 17046.0
170 17103.0
180 17162.0
190 17222.0

asahilina

Legend:

• (K)ernel or (U)ser
• (S)hared or (P)rivate
• (F)irmware or (G)PU or (X)Both

TVB Buffer heap:

Directly related to the buffer heap

• (KSF): Buffer info struct (maybe should be KPF?)
• (KSF): Block control pointers
• (KSF): Use counter

asahilina

asahilina

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.1.0-rc5 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="clang version 14.0.4"
CONFIG_GCC_VERSION=0
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=140004
CONFIG_AS_IS_LLVM=y
CONFIG_AS_VERSION=140004

asahilina

--- ./net/base/address_tracker_linux.cc.old	2023-03-06 23:53:08.102111285 +0900
+++ ./net/base/address_tracker_linux.cc	2023-03-06 23:53:13.112109094 +0900
@@ -334,7 +334,7 @@
   *address_changed = false;
   *link_changed = false;
   *tunnel_changed = false;
-  char buffer[4096];
+  char buffer[65536];
   bool first_loop = true;
   {

asahilina

## RGB10A8 2-plane

Texture
  Dimension: 2D
  Layout: Compressed
  Channels: unknown 4C (XXX)
  Type: XR
  Swizzle R: B
  Swizzle G: G
  Swizzle B: R

asahilina

-- As explained on: https://bennett.dev/auto-link-pipewire-ports-wireplumber/

-- Link two ports together
function link_port(output_port, input_port)
    if not input_port or not output_port then
        return nil
    end

    local link_args = {
        ["link.input.node"] = input_port.properties["node.id"],