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gistfile1.txt
#!/usr/bin/env python3
# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023, Alex Taradov <[email protected]>. All rights reserved.
#------------------------------------------------------------------------------
core_debug = {
'name': 'CD',
'description': 'Core Debug',
'base': 0xe000edf0,
'source': 'DDI0403D_arm_architecture_v7m_reference_manual.pdf',
'registers': [
('DHCSR', 0x00, 'RW', 'Debug Halting Control and Status Register', [
('DBGKEY', 16, 16),
('S_RESET_ST', 25, 1),
('S_RETIRE_ST', 24, 1),
('S_LOCKUP', 19, 1),
('S_SLEEP', 18, 1),
('S_HALT', 17, 1),
('S_REGRDY', 16, 1),
('C_SNAPSTALL', 5, 1),
('C_MASKINTS', 3, 1),
('C_STEP', 2, 1),
('C_HALT', 1, 1),
('C_DEBUGEN', 0, 1),
]),
('DCRSR', 0x04, 'W', 'Debug Core Register Selector Register', [
('REGWnR', 16, 1),
('REGSEL', 0, 5),
]),
('DCRDR', 0x08, 'RW', 'Debug Core Register Data Register'),
('DEMCR', 0x0C, 'RW', 'Debug Exception and Monitor Control Register', [
('TRCENA', 24, 1),
('MON_REQ', 19, 1),
('MON_STEP', 18, 1),
('MON_PEND', 17, 1),
('MON_EN', 16, 1),
('VC_HARDERR', 10, 1),
('VC_INTERR', 9, 1),
('VC_BUSERR', 8, 1),
('VC_STATERR', 7, 1),
('VC_CHKERR', 6, 1),
('VC_NOCPERR', 5, 1),
('VC_MMERR', 4, 1),
('VC_CORERESET', 0, 1),
]),
],
'defines': [
('CD_DHCSR_DBGKEY_VALUE', 0xa05f0000),
]
}
#------------------------------------------------------------------------------
breakpoint = {
'name': 'FP',
'description': 'Flash Patch and Breakpoint',
'base': 0xe0002000,
'source': 'DDI0403E_B_armv7m_arm.pdf',
'registers': [
('CTRL', 0x00, 'RW', 'FlashPatch Control Register', [
('REV', 28, 4),
('NUM_CODE1', 12, 3),
('NUM_LIT', 8, 4),
('NUM_CODE0', 4, 4),
('KEY', 1, 1),
('ENABLE', 0, 1),
]),
('REMAP', 0x04, 'RW', 'FlashPatch Remap Register', [
('RMPSPT', 29, 1),
('REMAP', 5, 24),
]),
('COMP', 0x08, 'RW', 'FlashPatch Comparator Register', (128, 4), [
('REPLACE', 30, 2),
('COMP', 2, 27),
('ENABLE', 0, 1),
]),
# 'LSR', 0xfb4, 'RO'
# 'ID space', 0xfd0 - 0xffc, 'RO'
],
}
#------------------------------------------------------------------------------
itm = {
'name': 'ITM',
'description': 'Instrumentation Trace Macrocell',
'base': 0xe0000000,
'source': '',
'registers': [
('PORT', 0x000, 'RW', 'ITM Stimulus Port', (32, 4)),
('TER', 0xe00, 'RW', 'ITM Trace Enable Register'),
('TPR', 0xe40, 'RW', 'ITM Trace Privilege Register'),
('TCR', 0xe80, 'RW', 'ITM Trace Control Register', [
('BUSY', 23, 1),
('TraceBusID', 16, 7),
('GTSFREQ', 10, 2),
('TSPrescale', 8, 2),
('SWOENA', 4, 1),
('DWTENA', 3, 1),
('SYNCENA', 2, 1),
('TSENA', 1, 1),
('ITMENA', 0, 1),
]),
('IWR', 0xef8, 'W', 'ITM Integration Write Register', [
('ATVALIDM', 0, 1),
]),
('IRR', 0xefc, 'R', 'ITM Integration Read Register', [
('ATREADYM', 0, 1),
]),
('IMCR', 0xf00, 'RW', 'ITM Integration Mode Control Register', [
('INTEGRATION', 0, 1),
]),
('LAR', 0xfb0, 'W', 'ITM Lock Access Register'),
('LSR', 0xfb4, 'R', 'ITM Lock Status Register', [
('ByteAcc', 2, 1),
('Access', 1, 1),
('Present', 0, 1),
]),
],
'defines': [
('ITM_LAR_KEY_UNLOCK', 0xc5acce55),
]
}
#------------------------------------------------------------------------------
dwt = {
'name': 'DWT',
'description': 'Data Watchpoint and Trace',
'base': 0xe0001000,
'source': '',
'registers': [
('CTRL', 0x000, 'RW', 'Control Register', [
('NUMCOMP', 28, 4),
('NOTRCPKT', 27, 1),
('NOEXTTRIG', 26, 1),
('NOCYCCNT', 25, 1),
('NOPRFCNT', 24, 1),
('CYCEVTENA', 22, 1),
('FOLDEVTENA', 21, 1),
('LSUEVTENA', 20, 1),
('SLEEPEVTENA', 19, 1),
('EXCEVTENA', 18, 1),
('CPIEVTENA', 17, 1),
('EXCTRCENA', 16, 1),
('PCSAMPLENA', 12, 1),
('SYNCTAP', 10, 2),
('CYCTAP', 9, 1),
('POSTINIT', 5, 4),
('POSTPRESET', 1, 4),
('CYCCNTENA', 0, 1),
]),
('CYCCNT', 0x004, 'RW', 'Cycle Count Register'),
('CPICNT', 0x008, 'RW', 'CPI Count Register'),
('EXCCNT', 0x00c, 'RW', 'Exception Overhead Count Register'),
('SLEEPCNT', 0x010, 'RW', 'Sleep Count Register'),
('LSUCNT', 0x014, 'RW', 'LSU Count Register'),
('FOLDCNT', 0x018, 'RW', 'Folded-instruction Count Register'),
('PCSR', 0x01c, 'R', 'Program Counter Sample Register'),
('COMP', 0x020, 'RW', 'Comparator Register', (4, 0x10)),
('MASK', 0x024, 'RW', 'Mask Register', (4, 0x10), [
('MASK', 0, 5),
]),
('FUNCTION', 0x028, 'RW', 'Function Register', (4, 0x10), [
('MATCHED', 24, 1),
('DATAVADDR1', 16, 4),
('DATAVADDR0', 12, 4),
('DATAVSIZE', 10, 2),
('LNK1ENA', 9, 1),
('DATAVMATCH', 8, 1),
('CYCMATCH', 7, 1),
('EMITRANGE', 5, 1),
('FUNCTION', 0, 4),
]),
('LAR', 0xfb0, 'W', 'Lock Access Register'),
('LSR', 0xfb4, 'R', 'Lock Status Register'),
],
'defines': [
('DWT_LAR_KEY_UNLOCK', 0xc5acce55),
]
}
#------------------------------------------------------------------------------
tpi = {
'name': 'TPI',
'description': 'Trace Port Interface',
'base': 0xe0040000,
'source': 'DDI0314H_coresight_components_trm.pdf',
'registers': [
('SSPSR', 0x000, 'R', 'Supported Parallel Port Size Register'),
('CSPSR', 0x004, 'RW', 'Current Parallel Port Size Register'),
('ACPR', 0x010, 'RW', 'Asynchronous Clock Prescaler Register', [
('PRESCALER', 0, 13),
]),
('SPPR', 0x0f0, 'RW', 'Selected Pin Protocol Register', [
('TXMODE', 0, 2),
]),
('FFSR', 0x300, 'R', 'Formatter and Flush Status Register', [
('FtNonStop', 3, 1),
('TCPresent', 2, 1),
('FtStopped', 1, 1),
('FlInProg', 0, 1),
]),
('FFCR', 0x304, 'RW', 'Formatter and Flush Control Register', [
('TrigIn', 8, 1),
('EnFCont', 1, 1),
]),
('FSCR', 0x308, 'R', 'Formatter Synchronization Counter Register'),
('TRIGGER', 0xee8, 'R', 'TRIGGER Register', [
('TRIGGER', 0, 1),
]),
('FIFO0', 0xeec, 'R', 'Integration ETM Data', [
#define TPI_FIFO0_ITM_ATVALID 29U /*!< TPI FIFO0: ITM_ATVALID Position'),
#define TPI_FIFO0_ITM_ATVALID (0x3UL << TPI_FIFO0_ITM_ATVALID) /*!< TPI FIFO0: ITM_ATVALID Mask'),
#define TPI_FIFO0_ITM_bytecount 27U /*!< TPI FIFO0: ITM_bytecount Position'),
#define TPI_FIFO0_ITM_bytecount (0x3UL << TPI_FIFO0_ITM_bytecount) /*!< TPI FIFO0: ITM_bytecount Mask'),
#define TPI_FIFO0_ETM_ATVALID 26U /*!< TPI FIFO0: ETM_ATVALID Position'),
#define TPI_FIFO0_ETM_ATVALID (0x3UL << TPI_FIFO0_ETM_ATVALID) /*!< TPI FIFO0: ETM_ATVALID Mask'),
#define TPI_FIFO0_ETM_bytecount 24U /*!< TPI FIFO0: ETM_bytecount Position'),
#define TPI_FIFO0_ETM_bytecount (0x3UL << TPI_FIFO0_ETM_bytecount) /*!< TPI FIFO0: ETM_bytecount Mask'),
#define TPI_FIFO0_ETM2 16U /*!< TPI FIFO0: ETM2 Position'),
#define TPI_FIFO0_ETM2 (0xFFUL << TPI_FIFO0_ETM2) /*!< TPI FIFO0: ETM2 Mask'),
#define TPI_FIFO0_ETM1 8U /*!< TPI FIFO0: ETM1 Position'),
#define TPI_FIFO0_ETM1 (0xFFUL << TPI_FIFO0_ETM1) /*!< TPI FIFO0: ETM1 Mask'),
#define TPI_FIFO0_ETM0 0U /*!< TPI FIFO0: ETM0 Position'),
#define TPI_FIFO0_ETM0 (0xFFUL /*<< TPI_FIFO0_ETM0*/) /*!< TPI FIFO0: ETM0 Mask'),
]),
('ITATBCTR2', 0xef0, 'R', 'ITATBCTR2', [
('AFVALIDS', 1, 1),
('ATREADYS', 0, 1),
]),
('ITATBCTR0', 0xef8, 'R', 'ITATBCTR0', [
('ATVALID', 0, 1),
]),
('FIFO1', 0xefc, 'R', 'Integration ITM Data', [
#define TPI_FIFO1_ITM_ATVALID (0x3UL << TPI_FIFO1_ITM_ATVALID) /*!< TPI FIFO1: ITM_ATVALID Mask'),
#define TPI_FIFO1_ITM_bytecount 27U /*!< TPI FIFO1: ITM_bytecount Position'),
#define TPI_FIFO1_ITM_bytecount (0x3UL << TPI_FIFO1_ITM_bytecount) /*!< TPI FIFO1: ITM_bytecount Mask'),
#define TPI_FIFO1_ETM_ATVALID 26U /*!< TPI FIFO1: ETM_ATVALID Position'),
#define TPI_FIFO1_ETM_ATVALID (0x3UL << TPI_FIFO1_ETM_ATVALID) /*!< TPI FIFO1: ETM_ATVALID Mask'),
#define TPI_FIFO1_ETM_bytecount 24U /*!< TPI FIFO1: ETM_bytecount Position'),
#define TPI_FIFO1_ETM_bytecount (0x3UL << TPI_FIFO1_ETM_bytecount) /*!< TPI FIFO1: ETM_bytecount Mask'),
#define TPI_FIFO1_ITM2 16U /*!< TPI FIFO1: ITM2 Position'),
#define TPI_FIFO1_ITM2 (0xFFUL << TPI_FIFO1_ITM2) /*!< TPI FIFO1: ITM2 Mask'),
#define TPI_FIFO1_ITM1 8U /*!< TPI FIFO1: ITM1 Position'),
#define TPI_FIFO1_ITM1 (0xFFUL << TPI_FIFO1_ITM1) /*!< TPI FIFO1: ITM1 Mask'),
#define TPI_FIFO1_ITM0 0U /*!< TPI FIFO1: ITM0 Position'),
#define TPI_FIFO1_ITM0 (0xFFUL /*<< TPI_FIFO1_ITM0*/) /*!< TPI FIFO1: ITM0 Mask'),
]),
('ITCTRL', 0xf00, 'RW', 'Integration Mode Control', [
('Mode', 0, 2),
]),
('CLAIMSET', 0xfa0, 'RW', 'Claim tag set'),
('CLAIMCLR', 0xfa4, 'RW', 'Claim tag clear'),
('DEVID', 0xfc8, 'R', 'DEVID', [
('NRZVALID', 11, 1),
('MANCVALID', 10, 1),
('PTINVALID', 9, 1),
('MinBufSz', 6, 3),
('AsynClkIn', 5, 1),
('NrTraceInput', 0, 1),
]),
('DEVTYPE', 0xfcc, 'R', 'DEVTYPE', [
('SubType', 4, 4),
('MajorType', 0, 4),
]),
]
}
#------------------------------------------------------------------------------
scb = {
'name': 'SCB',
'description': 'System Control Block',
'base': 0xe000ed00,
'source': '',
'registers': [
('CPUID', 0x000, 'R', 'CPUID Base Register', [
('IMPLEMENTER', 24, 8),
('VARIANT', 20, 4),
('ARCHITECTURE', 16, 4),
('PARTNO', 4, 12),
('REVISION', 0, 4),
]),
('ICSR', 0x004, 'RW', 'Interrupt Control and State Register', [
('NMIPENDSET', 31, 1),
('PENDSVSET', 28, 1),
('PENDSVCLR', 27, 1),
('PENDSTSET', 26, 1),
('PENDSTCLR', 25, 1),
('ISRPREEMPT', 23, 1),
('ISRPENDING', 22, 1),
('VECTPENDING', 12, 9),
('RETTOBASE', 11, 1),
('VECTACTIVE', 0, 9),
]),
('VTOR', 0x008, 'RW', 'Vector Table Offset Register'),
('AIRCR', 0x00C, 'RW', 'Application Interrupt and Reset Control Register', [
('VECTKEY', 16, 16),
('ENDIANESS', 15, 1),
('PRIGROUP', 8, 3),
('SYSRESETREQ', 2, 1),
('VECTCLRACTIVE', 1, 1),
('VECTRESET', 0, 1),
]),
('SCR', 0x010, 'RW', 'System Control Register', [
('SEVONPEND', 4, 1),
('SLEEPDEEP', 2, 1),
('SLEEPONEXIT', 1, 1),
]),
('CCR', 0x014, 'RW', 'Configuration Control Register', [
('BP', 18, 1),
('IC', 17, 1),
('DC', 16, 1),
('STKALIGN', 9, 1),
('BFHFNMIGN', 8, 1),
('DIV_0_TRP', 4, 1),
('UNALIGN_TRP', 3, 1),
('USERSETMPEND', 1, 1),
('NONBASETHRDENA', 0, 1),
]),
('SHPR', 0x018, 'RW', 'System Handlers Priority Registers (4-7, 8-11, 12-15)', (3, 4)),
('SHCSR', 0x024, 'RW', 'System Handler Control and State Register', [
('USGFAULTENA', 18, 1),
('BUSFAULTENA', 17, 1),
('MEMFAULTENA', 16, 1),
('SVCALLPENDED', 15, 1),
('BUSFAULTPENDED', 14, 1),
('MEMFAULTPENDED', 13, 1),
('USGFAULTPENDED', 12, 1),
('SYSTICKACT', 11, 1),
('PENDSVACT', 10, 1),
('MONITORACT', 8, 1),
('SVCALLACT', 7, 1),
('USGFAULTACT', 3, 1),
('BUSFAULTACT', 1, 1),
('MEMFAULTACT', 0, 1),
]),
('CFSR', 0x028, 'RW', 'Configurable Fault Status Register', [
('DIVBYZERO', 25, 1),
('UNALIGNED', 24, 1),
('NOCP', 19, 1),
('INVPC', 18, 1),
('INVSTATE', 17, 1),
('UNDEFINSTR', 16, 1),
('BFARVALID', 15, 1),
('LSPERR', 13, 1),
('STKERR', 12, 1),
('UNSTKERR', 11, 1),
('IMPRECISERR', 10, 1),
('PRECISERR', 9, 1),
('IBUSERR', 8, 1),
('MMARVALID', 7, 1),
('MLSPERR', 5, 1),
('MSTKERR', 4, 1),
('MUNSTKERR', 3, 1),
('DACCVIOL', 1, 1),
('IACCVIOL', 0, 1),
]),
('HFSR', 0x02C, 'RW', 'HardFault Status Register', [
('DEBUGEVT', 31, 1),
('FORCED', 30, 1),
('VECTTBL', 1, 1),
]),
('DFSR', 0x030, 'RW', 'Debug Fault Status Register', [
('EXTERNAL', 4, 1),
('VCATCH', 3, 1),
('DWTTRAP', 2, 1),
('BKPT', 1, 1),
('HALTED', 0, 1),
]),
('MMFAR', 0x034, 'RW', 'MemManage Fault Address Register'),
('BFAR', 0x038, 'RW', 'BusFault Address Register'),
('AFSR', 0x03C, 'RW', 'Auxiliary Fault Status Register'),
('ID_PFR', 0x040, 'R', 'Processor Feature Register', (2, 4)),
('ID_DFR', 0x048, 'R', 'Debug Feature Register'),
('ID_AFR', 0x04C, 'R', 'Auxiliary Feature Register'),
('ID_MFR', 0x050, 'R', 'Memory Model Feature Register', (4, 4)),
('ID_ISAR', 0x060, 'R', 'Instruction Set Attributes Register', (5, 4)),
('CLIDR', 0x078, 'R', 'Cache Level ID register', [
('LOUU', 27, 3),
('LOC', 24, 3),
]),
('CTR', 0x07C, 'R', 'Cache Type register', [
('FORMAT', 29, 3),
('CWG', 24, 4),
('ERG', 20, 4),
('DMINLINE', 16, 4),
('IMINLINE', 0, 4),
]),
('CCSIDR', 0x080, 'R', 'Cache Size ID Register', [
('WT', 31, 1),
('WB', 30, 1),
('RA', 29, 1),
('WA', 28, 1),
('NUMSETS', 13, 15),
('ASSOCIATIVITY', 3, 10),
('LINESIZE', 0, 3),
]),
('CSSELR', 0x084, 'RW', 'Cache Size Selection Register', [
('LEVEL', 1, 3),
('IND', 0, 1),
]),
('CPACR', 0x088, 'RW', 'Coprocessor Access Control Register'),
('STIR', 0x200, 'W', 'Software Triggered Interrupt Register', [
('INTID', 0, 9),
]),
('MVFR0', 0x240, 'R', 'Media and VFP Feature Register 0'),
('MVFR1', 0x244, 'R', 'Media and VFP Feature Register 1'),
('MVFR2', 0x248, 'R', 'Media and VFP Feature Register 2'),
('ICIALLU', 0x250, 'W', 'I-Cache Invalidate All to PoU'),
('ICIMVAU', 0x258, 'W', 'I-Cache Invalidate by MVA to PoU'),
('DCIMVAC', 0x25C, 'W', 'D-Cache Invalidate by MVA to PoC'),
('DCISW', 0x260, 'W', 'D-Cache Invalidate by Set-way', [
('WAY', 30, 2),
('SET', 5, 9),
]),
('DCCMVAU', 0x264, 'W', 'D-Cache Clean by MVA to PoU'),
('DCCMVAC', 0x268, 'W', 'D-Cache Clean by MVA to PoC'),
('DCCSW', 0x26C, 'W', 'D-Cache Clean by Set-way', [
('WAY', 30, 2),
('SET', 5, 9),
]),
('DCCIMVAC', 0x270, 'W', 'D-Cache Clean and Invalidate by MVA to PoC'),
('DCCISW', 0x274, 'W', 'D-Cache Clean and Invalidate by Set-way', [
('WAY', 30, 2),
('SET', 5, 9),
]),
('ITCMCR', 0x290, 'RW', 'Instruction Tightly-Coupled Memory Control Register', [
('SZ', 3, 4),
('RETEN', 2, 1),
('RMW', 1, 1),
('EN', 0, 1),
]),
('DTCMCR', 0x294, 'RW', 'Data Tightly-Coupled Memory Control Registers', [
('SZ', 3, 4),
('RETEN', 2, 1),
('RMW', 1, 1),
('EN', 0, 1),
]),
('AHBPCR', 0x298, 'RW', 'AHBP Control Register', [
('SZ', 1, 3),
('EN', 0, 1),
]),
('CACR', 0x29C, 'RW', 'L1 Cache Control Register', [
('FORCEWT', 2, 1),
('ECCEN', 1, 1),
('SIWT', 0, 1),
]),
('AHBSCR', 0x2A0, 'RW', 'AHB Slave Control Register', [
('INITCOUNT', 11, 5),
('TPRI', 2, 9),
('CTL', 0, 2),
]),
('ABFSR', 0x2A8, 'RW', 'Auxiliary Bus Fault Status Register', [
('AXIMTYPE', 8, 2),
('EPPB', 4, 1),
('AXIM', 3, 1),
('AHBP', 2, 1),
('DTCM', 1, 1),
('ITCM', 0, 1),
]),
],
'defines': [
('SCB_AIRCR_VECTKEY_VALUE', 0x05fa0000),
]
}
#------------------------------------------------------------------------------
scnscb = {
'name': 'SCnSCB',
'description': 'System Controls not in SCB',
'base': 0xe000e000,
'source': '',
'registers': [
('ICTR', 0x04, 'R', 'Interrupt Controller Type Register', [
('INTLINESNUM', 0, 4),
]),
('ACTLR', 0x08, 'RW', 'Auxiliary Control Register', [
('DISITMATBFLUSH', 12, 1),
('DISRAMODE', 11, 1),
('FPEXCODIS', 10, 1),
('DISFOLD', 2, 1),
('DISMCYCINT', 0, 1),
]),
]
}
#------------------------------------------------------------------------------
etm_v4 = {
'name': 'ETM',
'description': 'Embedded Trace Macrocell v4',
'base': 0xe0041000,
'source': 'IHI0064D_etm_v4_architecture_spec.pdf', # Note: was 'DDI0494D_coresight_etm_m7_r0p1_trm.pdf'
'registers': [
'General control and ID registers',
('TRCPRGCTLR', 0x04, 'RW', 'Trace Programming Control Register', [
('EN', 0, 1),
]),
('TRCPROCSELR', 0x08, 'RW', 'Trace PE Select Control Register', [
('PROCSEL', 0, 3),
]),
('TRCSTATR', 0x0C, 'R', 'Trace Trace Status Register', [
('PMSTABLE', 1, 1),
('IDLE', 0, 1),
]),
('TRCCONFIGR', 0x10, 'RW', 'Trace Trace Configuration Register', [
('DV', 17, 1),
('DA', 16, 1),
('VMIDOPT', 15, 1),
('RS', 12, 1),
('TS', 11, 1),
('COND', 8, 3),
('VMID', 7, 1),
('CID', 6, 1),
('CCI', 4, 1),
('BB', 3, 1),
('INSTP0', 1, 2),
]),
('TRCAUXCTLR', 0x18, 'RW', 'Trace Auxiliary Control Register'),
('TRCEVENTCTL0R', 0x20, 'RW', 'Trace Event Control 0 Register', [
('EVENT3', 24, 8),
('EVENT2', 16, 8),
('EVENT1', 8, 8),
('EVENT0', 0, 8),
]),
('TRCEVENTCTL1R', 0x24, 'RW', 'Trace Event Control 1 Register', [
('LPOVERRIDE', 12, 1),
('ATB', 11, 1),
('DATAEN', 4, 1),
('INSTEN', 0, 4),
]),
('TRCSTALLCTLR', 0x2C, 'RW', 'Trace Stall Control Register', [
('NOOVERFLOW', 13, 1),
('DATADISCARD', 11, 2),
('INSTPRIORITY', 10, 1),
('DSTALL', 9, 1),
('ISTALL', 8, 1),
('LEVEL', 0, 4),
]),
('TRCTSCTLR', 0x30, 'RW', 'Trace Global Timestamp Control Register', [
('EVENT', 0, 8),
]),
('TRCSYNCPR', 0x34, 'RW', 'Trace Synchronization Period Register', [
('PERIOD', 0, 5),
]),
('TRCCCCTLR', 0x38, 'RW', 'Trace Cycle Count Control Register', [
('THRESHOLD', 0, 12),
]),
('TRCBBCTLR', 0x3C, 'RW', 'Trace Branch Broadcast Control Register', [
('MODE', 8, 1),
('RANGE', 0, 8),
]),
('TRCTRACEIDR', 0x40, 'RW', 'Trace Trace ID Register', [
('TRACEID', 0, 8),
]),
('TRCQCTLR', 0x44, 'RW', 'Trace Q Element Control Register', [
('MODE', 8, 1),
('RANGE', 0, 8),
]),
'Trace filtering control registers',
('TRCVICTLR', 0x80, 'RW', 'Trace ViewInst Main Control Register', [
('EXLEVEL_NS', 20, 4),
('EXLEVEL_S', 16, 4),
('TRCERR', 11, 1),
('TRCRESET', 10, 1),
('SSSTATUS', 9, 1),
('EVENT', 0, 8),
]),
('TRCVIIECTLR', 0x84, 'RW', 'Trace ViewInst Include/Exclude Control Register', [
('EXCLUDE', 16, 16),
('INCLUDE', 0, 16),
]),
('TRCVISSCTLR', 0x88, 'RW', 'Trace ViewInst Start/Stop Control Register', [
('STOP', 16, 16),
('START', 0, 16),
]),
('TRCVIPCSSCTLR', 0x8C, 'RW', 'Trace ViewInst Start/Stop PE Comparator Control Register', [
('STOP', 16, 16),
('START', 0, 16),
]),
('TRCVDCTLR', 0xA0, 'RW', 'Trace ViewData Main Control Register', [
('TRCEXDATA', 12, 1),
('TBI', 11, 1),
('PCREL', 10, 1),
('SPREL', 8, 2),
('EVENT', 0, 8),
]),
('TRCVDSACCTLR', 0xA4, 'RW', 'Trace ViewData Include/Exclude Single Address Comparator Control Register', [
('EXCLUDE', 16, 16),
('INCLUDE', 0, 16),
]),
('TRCVDARCCTLR', 0xA8, 'RW', 'Trace ViewData Include/Exclude Address Range Comparator Control Register', [
('EXCLUDE', 16, 16),
('INCLUDE', 0, 16),
]),
'Derived resource registers',
('TRCSEQEVR', 0x100, 'RW', 'Trace Sequencer State Transition Control Register [n=0-2]', (3, 4), [
('B', 8, 8),
('F', 0, 8),
]),
('TRCSEQRSTEVR', 0x118, 'RW', 'Trace Sequencer Reset Control Register', [
('RST', 0, 8),
]),
('TRCSEQSTR', 0x11C, 'RW', 'Trace Sequencer State Register', [
('STATE', 0, 2),
]),
('TRCEXTINSELR', 0x120, 'RW', 'Trace External Input Select Register', [
('SEL3', 24, 8),
('SEL2', 16, 8),
('SEL1', 8, 8),
('SEL0', 0, 8),
]),
('TRCCNTRLDVR', 0x140, 'RW', 'Trace Counter Reload Value Register [n=0-3]', (4, 4), [
('VALUE', 0, 16),
]),
('TRCCNTCTLR', 0x150, 'RW', 'Trace Counter Control Register [n=0-3]', (4, 4), [
('CNTCHAIN', 17, 1),
('RLDSELF', 16, 1),
('RLDEVENT', 8, 8),
('CNTEVENT', 0, 8),
]),
('TRCCNTVR', 0x160, 'RW', 'Trace Counter Value Register [n=0-3]', (4, 4), [
('VALUE', 0, 16),
]),
'Implementation specific and identification registers',
('TRCIDR8', 0x180, 'R', 'Trace ID Register 8', [
('MAXSPEC', 0, 32),
]),
('TRCIDR9', 0x184, 'R', 'Trace ID Register 9', [
('NUMP0KEY', 0, 32),
]),
('TRCIDR10', 0x188, 'R', 'Trace ID Register 10', [
('NUMP1KEY', 0, 32),
]),
('TRCIDR11', 0x18C, 'R', 'Trace ID Register 11', [
('NUMP1SPC', 0, 32),
]),
('TRCIDR12', 0x190, 'R', 'Trace ID Register 12', [
('NUMCONDKEY', 0, 32),
]),
('TRCIDR13', 0x194, 'R', 'Trace ID Register 13', [
('NUMCONDSPC', 0, 32),
]),
('TRCIDR0', 0x1E0, 'R', 'Trace ID Register 0', [
('COMMOPT', 29, 1),
('TSSIZE', 24, 5),
('TRCEXDATA', 17, 1),
('QSUPP', 15, 2),
('QFILT', 14, 1),
('CONDTYPE', 12, 2),
('NUMEVENT', 10, 2),
('RETSTACK', 9, 1),
('TRCCCI', 7, 1),
('TRCCOND', 6, 1),
('TRCBB', 5, 1),
('TRCDATA', 3, 2),
('INSTP0', 1, 2),
]),
('TRCIDR1', 0x1E4, 'R', 'Trace ID Register 1', [
('DESIGNER', 24, 8),
('TRCARCHMAJ', 8, 4),
('TRCARCHMIN', 4, 4),
('REVISION', 0, 4),
]),
('TRCIDR2', 0x1E8, 'R', 'Trace ID Register 2', [
('VMIDOPT', 29, 2),
('CCSIZE', 25, 4),
('DVSIZE', 20, 5),
('DASIZE', 15, 5),
('VMIDSIZE', 10, 5),
('CIDSIZE', 5, 5),
('IASIZE', 0, 5),
]),
('TRCIDR3', 0x1EC, 'R', 'Trace ID Register 3', [
('NOOVERFLOW', 31, 1),
('NUMPROC_L', 28, 3),
('SYSSTALL', 27, 1),
('STALLCTL', 26, 1),
('SYNCPR', 25, 1),
('TRCERR', 24, 1),
('EXLEVEL_NS', 20, 4),
('EXLEVEL_S', 16, 4),
('NUMPROC_H', 12, 2),
('CCITMIN', 0, 12),
]),
('TRCIDR4', 0x1F0, 'R', 'Trace ID Register 4', [
('NUMVMIDC', 28, 4),
('NUMCIDC', 24, 4),
('NUMSSCC', 20, 4),
('NUMRSPAIR', 16, 4),
('NUMPC', 12, 4),
('SUPPDAC', 8, 1),
('NUMDVC', 4, 4),
('NUMACPAIRS', 0, 4),
]),
('TRCIDR5', 0x1F4, 'R', 'Trace ID Register 5', [
('REDFUNCNTR', 31, 1),
('NUMCNTR', 28, 3),
('NUMSEQSTATE', 25, 3),
('LPOVERRIDE', 23, 1),
('ATBTRIG', 22, 1),
('TRACEIDSIZE', 16, 6),
('NUMEXTINSEL', 9, 3),
('NUMEXTIN', 0, 9),
]),
('TRCIDR6', 0x1F8, 'R', 'Trace ID Register 6'),
('TRCIDR7', 0x1FC, 'R', 'Trace ID Register 7'),
('TRCIMSPEC', 0x1C0, 'RW', 'Trace Implementation Defined registers [n=0-7]', (8, 4)),
'Resource selection registers',
('TRCRSCTLR', 0x200, 'RW', 'Trace Resource Selection Control Register [n=2-31]', (32, 4), [
('PAIRINV', 21, 1),
('INV', 20, 1),
('GROUP', 16, 4),
('SELECT', 0, 16),
]),
'Single-shot comparator registers',
('TRCSSCCR', 0x280, 'RW', 'Trace Single-shot Comparator Control Register [n=0-7]', (8, 4), [
('RST', 24, 1),
('ARC', 16, 8),
('SAC', 0, 16),
]),
('TRCSSCSR', 0x2A0, 'RW', 'Trace Single-shot Comparator Status Register [n=0-7]', (8, 4), [
('STATUS', 31, 1),
('PC', 3, 1),
('DV', 2, 1),
('DA', 1, 1),
('INST', 0, 1),
]),
('TRCSSPCICR', 0x2C0, 'RW', 'Trace Single-shot PE Comparator Input Control Register [n=0-7]', (8, 4), [
('PC', 0, 8),
]),
'Power control registers',
('TRCOSLAR', 0x300, 'W', 'Management OS Lock Access Register', [
('OSLK', 0, 1),
]),
('TRCOSLSR', 0x304, 'R', 'Management OS Lock Status Register', [
('OSLM1', 3, 1),
('NTT', 2, 1),
('OSLK', 1, 1),
('OSLM0', 0, 1),
]),
('TRCPDCR', 0x310, 'RW', 'Management PowerDown Control Register', [
('PU', 3, 1),
]),
('TRCPDSR', 0x314, 'R', 'Management PowerDown Status Register', [
('OSLK', 5, 1),
('STICKYPD', 1, 1),
('POWER', 0, 1),
]),
'Comparator registers',
('TRCACVR', 0x400, 'RW', 'Trace Address Comparator Value Register [n=0-15]', (16, 8)),
('TRCACATR', 0x480, 'RW', 'Trace Address Comparator Access Type Register [n=0-15]', (16, 8), [
('DTBM', 21, 1),
('DATARANGE', 20, 1),
('DATASIZE', 18, 2),
('DATAMATCH', 16, 2),
('EXLEVEL_NS', 12, 4),
('EXLEVEL_S', 8, 4),
('CONTEXT', 4, 3),
('CONTEXTTYPE', 2, 2),
('TYPE', 0, 2),
]),
('TRCDVCVR', 0x500, 'RW', 'Trace Data Value Comparator Value Register [n=0-7]', (8, 16)),
('TRCDVCMR', 0x580, 'RW', 'Trace Data Value Comparator Mask Register [n=0-7]', (8, 16)),
('TRCCIDCVR', 0x600, 'RW', 'Trace Context ID Comparator Value Register [n=0-7]', (8, 8)),
('TRCVMIDCVR', 0x640, 'RW', 'Trace Virtual context identifier Comparator Value Register [n=0-7]', (8, 8)),
('TRCCIDCCTLR0', 0x680, 'RW', 'Trace Context ID Comparator Control Register 0', [
('COMP3', 24, 8),
('COMP2', 16, 8),
('COMP1', 8, 8),
('COMP0', 0, 8),
]),
('TRCCIDCCTLR1', 0x684, 'RW', 'Trace Context ID Comparator Control Register 1', [
('COMP7', 24, 8),
('COMP6', 16, 8),
('COMP5', 8, 8),
('COMP4', 0, 8),
]),
('TRCVMIDCCTLR0', 0x688, 'RW', 'Trace Virtual context identifier Comparator Control Register 0', [
('COMP3', 24, 8),
('COMP2', 16, 8),
('COMP1', 8, 8),
('COMP0', 0, 8),
]),
('TRCVMIDCCTLR1', 0x68C, 'RW', 'Trace Virtual context identifier Comparator Control Register 1', [
('COMP3', 24, 8),
('COMP2', 16, 8),
('COMP1', 8, 8),
('COMP0', 0, 8),
]),
'CoreSight management registers',
('TRCITCTRL', 0xF00, 'RW', 'Management Integration Mode Control register', [
('IME', 0, 1),
]),
('TRCCLAIMSET', 0xFA0, 'RW', 'Trace Claim Tag Set register', [
('SET', 0, 8),
]),
('TRCCLAIMCLR', 0xFA4, 'RW', 'Trace Claim Tag Clear register', [
('CLR', 0, 8),
]),
('TRCDEVAFF0', 0xFA8, 'R', 'Management Device Affinity register 0', [
('U', 30, 1),
('UNK', 25, 5),
('MT', 24, 1),
('AFF2', 16, 8),
('AFF1', 8, 8),
('AFF0', 0, 8),
]),
('TRCDEVAFF1', 0xFAC, 'R', 'Management Device Affinity register 1', [
('AFF3', 0, 8),
]),
('TRCLAR', 0xFB0, 'RW', 'Management Software Lock Access Register'),
('TRCLSR', 0xFB4, 'R', 'Management Software Lock Status Register', [
('NTT', 2, 1),
('SLK', 1, 1),
('SLI', 0, 1),
]),
('TRCAUTHSTATUS', 0xFB8, 'R', 'Management Authentication Status register', [
('HNID', 10, 2),
('HID', 8, 2),
('SNID', 6, 2),
('SID', 4, 2),
('NSNID', 2, 2),
('NSID', 0, 2),
]),
('TRCDEVARCH', 0xFBC, 'R', 'Management Device Architecture register', [
('ARCHITECT', 21, 11),
('PRESENT', 20, 1),
('REVISION', 16, 4),
('ARCHID', 0, 16),
]),
('TRCDEVID', 0xFC8, 'R', 'Management Device ID register'),
('TRCDEVTYPE', 0xFCC, 'R', 'Management Device Type register', [
('SUB', 4, 4),
('MAJOR', 0, 4),
]),
('TRCPIDR4', 0xFD0, 'R', 'Management Peripheral ID4 Register'),
('TRCPIDR5', 0xFD4, 'R', 'Management Peripheral ID5 Register'),
('TRCPIDR6', 0xFD8, 'R', 'Management Peripheral ID6 Register'),
('TRCPIDR7', 0xFDC, 'R', 'Management Peripheral ID7 Register'),
('TRCPIDR0', 0xFE0, 'R', 'Management Peripheral ID0 Register'),
('TRCPIDR1', 0xFE4, 'R', 'Management Peripheral ID1 Register'),
('TRCPIDR2', 0xFE8, 'R', 'Management Peripheral ID2 Register'),
('TRCPIDR3', 0xFEC, 'R', 'Management Peripheral ID3 Register'),
('TRCCIDR0', 0xFF0, 'R', 'Management Component ID0 Register'),
('TRCCIDR1', 0xFF4, 'R', 'Management Component ID1 Register'),
('TRCCIDR2', 0xFF8, 'R', 'Management Component ID2 Register'),
('TRCCIDR3', 0xFFC, 'R', 'Management Component ID3 Register'),
('TRCPIDR', 0, 'R', 'Dummy 64-bit register. This represents TRCPIDRx combined.', [
('4KBCOUNT', 36, 4),
('CONTCODE', 32, 4),
('REVAND', 28, 4),
('CUST', 24, 4),
('REVISION', 19, 4),
('IDCODE', 12, 7),
('PART', 0, 12),
]),
],
'defines': [
('ETM_TRCLAR_KEY_UNLOCK', 0xc5acce55),
],
}
#------------------------------------------------------------------------------
rom_table = {
'name': 'ROM_TABLE',
'description': 'ROM Table',
'base': 0xe00ff000,
'source': 'DDI0403D_arm_architecture_v7m_reference_manual.pdf',
'registers': [
('ENTRY', 0x00, 'R', 'ROM Table Entry', (256, 4), [
('OFFSET', 12, 20),
('FORMAT', 1, 1),
('PRESENT', 0, 1),
]),
],
}
#------------------------------------------------------------------------------
coresight_ids = {
'name': 'CS_ID',
'description': 'CoreSight Infrastructure IDs',
'base': 0,
'source': 'IHI0029D_coresight_architecture_spec_v2_0.pdf',
'registers': [
('ITCTRL', 0xf00, 'RW', 'Integration Mode Control register'),
('CLAIMSET', 0xfa0, 'RW', 'Claim Tag Set register'),
('CLAIMCLR', 0xfa4, 'RW', 'Claim Tag Clear register'),
('DEVAFF0', 0xfa8, 'R', 'Device Affinity register 0'),
('DEVAFF1', 0xfac, 'R', 'Device Affinity register 1'),
('LAR', 0xfb0, 'W', 'Lock Access Register'),
('LSR', 0xfb4, 'R', 'Lock Status Register'),
('AUTHSTATUS', 0xfb8, 'R', 'Authentication Status register'),
('DEVARCH', 0xfbc, 'R', 'Device Architecture register'),
('DEVID2', 0xfc0, 'R', 'Device Configuration register 2'),
('DEVID1', 0xfc4, 'R', 'Device Configuration register 1'),
('DEVID', 0xfc8, 'R', 'Device Configuration register'),
('DEVTYPE', 0xfcc, 'R', 'Device Type Identifier register'),
('PID4', 0xfd0, 'R', 'Peripheral Identification Register #4'),
('PID5', 0xfd4, 'R', 'Peripheral Identification Register #5'),
('PID6', 0xfd8, 'R', 'Peripheral Identification Register #6'),
('PID7', 0xfdc, 'R', 'Peripheral Identification Register #7'),
('PID0', 0xfe0, 'R', 'Peripheral Identification Register #0'),
('PID1', 0xfe4, 'R', 'Peripheral Identification Register #1'),
('PID2', 0xfe8, 'R', 'Peripheral Identification Register #2'),
('PID3', 0xfec, 'R', 'Peripheral Identification Register #3'),
('CID0', 0xff0, 'R', 'Component Identification Register #0'),
('CID1', 0xff4, 'R', 'Component Identification Register #1'),
('CID2', 0xff8, 'R', 'Component Identification Register #2'),
('CID3', 0xffc, 'R', 'Component Identification Register #3'),
],
}
#------------------------------------------------------------------------------
def get_parameters(prefix, base, reg):
fields = []
is_array = False
array_dim = (0, 0)
if len(reg) == 4:
name, offset, rw, text = reg
elif len(reg) == 6:
is_array = True
name, offset, rw, text, array_dim, fields = reg
elif isinstance(reg[4], tuple):
is_array = True
name, offset, rw, text, array_dim = reg
else:
name, offset, rw, text, fields = reg
return (name, offset, rw, text, fields, is_array, array_dim)
#------------------------------------------------------------------------------
def gen_reg(prefix, base, reg):
if isinstance(reg, str):
print('')
print('// %s' % reg)
return
name, offset, rw, text, fields, is_array, array_dim = get_parameters(prefix, base, reg)
name = '%s_%s' % (prefix, name)
addr = base + offset
if is_array:
a_size, a_stride = array_dim
print('#define %-24s (0x%08x + (x)*0x%x) // [%d] - %-2s - %s' % (name + '(x)', addr, a_stride, a_size, rw, text))
else:
print('#define %-24s 0x%08x // 0x%02x - %-2s - %s' % (name, addr, offset, rw, text))
#------------------------------------------------------------------------------
def gen_fields(prefix, base, reg):
if isinstance(reg, str):
return
name, offset, rw, text, fields, is_array, array_dim = get_parameters(prefix, base, reg)
name = '%s_%s' % (prefix, name)
addr = base + offset
for field in fields:
f_name, f_index, f_size = field
field_name = '%s_%s' % (name, f_name)
mask = (1<<f_size)-1
if f_size == 1:
print('#define %-24s (1 << %d)' % (field_name, f_index))
print('#define %-24s (((x) >> %d) & 1)' % (field_name + '_v(x)', f_index))
else:
print('#define %-24s (((x) & 0x%x) << %d)' % (field_name + '(x)', mask, f_index))
print('#define %-24s (((x) >> %d) & 0x%x)' % (field_name + '_v(x)', f_index, mask))
if len(fields):
print('')
#------------------------------------------------------------------------------
def gen(data):
print('//--- %s (%s) Registers (%s) ---' % (data['description'], data['name'], data['source']))
for reg in data['registers']:
gen_reg(data['name'], data['base'], reg)
print('')
for reg in data['registers']:
gen_fields(data['name'], data['base'], reg)
if 'defines' in data:
for define in data['defines']:
name, value = define
if isinstance(value, int):
value = '0x%x' % value
print('#define %-24s %s' % (name, value))
#------------------------------------------------------------------------------
def main():
print('// This file is automatically generated by gen_headers.py')
print('#ifndef _DEBUG_REGS_H_')
print('#define _DEBUG_REGS_H_')
for module in [core_debug, breakpoint, itm, dwt, tpi, scb, scnscb, etm_v4, rom_table, coresight_ids]:
print('')
gen(module)
print('')
print('#endif // _DEBUG_REGS_H_')
print('')
#------------------------------------------------------------------------------
main()
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