matris.v

///4*4 matris
module topla();
    reg [3:0] matris1 [0:3][0:3];
    reg [3:0] matris2 [0:3][0:3];
    reg [4:0] sonuc [0:3][0:3];
    integer i, j, k=0;
    
    //matris olusturmak icin kullanilan kisim
    initial begin
         for( i = 0 ; i < 4; i = i+1 ) begin
             for( j = 0 ; j < 4; j = j+1 ) begin
			           matris1[i][j] = k;
			           matris2[i][j] = k;
			           k = k+1;
             end
         end
    end
    
    //matrislerin toplami
    //initial begin baslangic
    genvar m,n;
    generate
		    for (m = 0; m < 4; m = m+1) begin  
			      for (n = 0; n < 4; n = n+1) begin
				        four_bit_adder(.f(sonuc[m][n]), .a(matris1[m][n]), .b(matris2[m][n])); 
                                                  //ust satirda onceden yazdigimiz "+" isaretini
                                                  // binarye gore elle yazdigimiz moduklle degistiriyoruz.

			      end
		    end 
    endgenerate
endmodule

module cikar();
    reg [3:0] matris1 [0:3][0:3];
    reg [3:0] matris2 [0:3][0:3];
    reg [4:0] sonuc [0:3][0:3];
    integer i, j, k=0;
    
    initial begin
         for( i = 0 ; i < 3; i = i+1 ) begin
             for( j = 0 ; j < 3; j = j+1 ) begin
			           matris1[i][j] = k;
			           matris2[i][j] = k;
			           k = k+1;
             end
         end
    end
    genvar m,n;
    generate
		    for (m = 0; m < 3; m = m+1) begin  
			      for (n = 0; n < 3; n = n+1) begin
			          four_bit_substractor sub1(.sub(sonuc[m][n]),.inp1(matris1[m][n]),.inp2(matris2[m][n]));
                                             // ayni sekilde burada da cikarma islemini artik kendi fonksiyonumuzla yapiyoruz.
			      end
		    end 
    endgenerate
endmodule



module carp();
    reg [3:0] matris1 [0:3][0:3];
    reg [3:0] aramatris [0:3][0:3];
    reg [7:0] sonuc [0:3][0:3];
    integer i, j, k=0;
    initial begin
        for( i = 0 ; i < 3; i = i+1 ) begin
            for( j = 0 ; j < 3; j = j+1 ) begin
                matris1[i][j] = k;
                aramatris[i][j] = k;
                k = k+1;
            end
        end
    end
    
    
    reg [7:0] toplam;
    reg [7:0] gecici_toplam;
    //initial begin baslangic
    genvar m,n,p;
    generate
        for (m = 0; m < 3; m = m+1) begin  
            for (n = 0; j < 3; n = n+1) begin
                assign toplam = 0; 
                for (p = 0; p < 3; p = p+1) begin
                    multiply4bits mul1(.product(gecici_toplam),.inp1(matris1[m][p]),.inp2(aramatris[p][m]));
                    eleven_bit_adder add1(.f(toplam),.a(toplam),.b(gecici_toplam));
                             //atrık islec yuklemesi yerine uygulamaya kendi modullerimizle sonuclar
                             // buluyoruz.                   
                end
                assign sonuc[m][n] = toplam; 
           end
        end
    endgenerate
endmodule

//11 bit toplayici
module eleven_bit_adder(f, a, b);
  output [12:0] f;
  input [11:0] a;
  input [11:0] b;
  wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13;   
  HA HA1(f[0],x1,a[0],b[0]);
  FA FA1(f[1],x2,a[1],b[1],x1);
  FA FA2(f[2],x3,a[2],b[2],x2);
  FA FA3(f[3],x4,a[3],b[3],x3);
  FA FA4(f[4],x5,a[4],b[4],x4);
  FA FA5(f[5],x6,a[5],b[5],x5);
  FA FA6(f[6],x7,a[6],b[6],x6);
  FA FA7(f[7],x8,a[7],b[7],x7);
  FA FA8(f[8],x9,a[8],b[8],x8);
  FA FA9(f[9],x10,a[9],b[9],x9);
  FA FA10(f[10],x11,a[10],b[10],x10);
  FA FA11(f[11],x12,a[11],b[11],x11); 
  f[12] = x12;;
endmodule

//4 bit toplayici
module four_bit_adder(f, a, b);
  output [4:0] f;
  input [3:0] a;
  input [3:0] b;
  wire x1,x2,x3,x4;   
  HA HA1(f[0],x1,a[0],b[0]);
  FA FA1(f[1],x2,a[1],b[1],x1);
  FA FA2(f[2],x3,a[2],b[2],x2);
  FA FA3(f[3],x4,a[3],b[3],x3);
  f[4] = x4;
endmodule


module multiply4bits(product,inp1,inp2);

  output [7:0]product;
  input [3:0]inp1;
  input [3:0]inp2;
  
  wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;    

  assign product[0]= (inp1[0]&inp2[0]);             
  HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
  FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
  FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
  HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
  HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
  FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
  FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
  FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
  HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
  FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
  FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
  FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10); 

endmodule

module four_bit_substractor( sub  , inp1 , inp2 );
  input [ 3 : 0 ] inp1 , inp2;
  reg control M = 1;
  output [ 4 : 0 ] sub;
  wire count ;
  wire w4 , w5 , w6 , w7;
  xor( w8 , M , inp2[0] );
  xor( w9 , M , inp2[1] );
  xor( w10 , M , inp2[2] );
  xor( w11 , M , inp2[3] );
  FA f1( sub[0] , w4 , inp1[0] , w8 , M );
  FA f2( sub[1] , w5 , inp1[1] , w9 , w4 );
  FA f3( sub[2] , w6 , inp1[2] , w10 , w5 );
  FA f4( sub[3] , count , inp1[3] , w11 , w6 );
  sub[4] = count;
endmodule


module HA(sout,cout,a,b);

  output sout,cout;
  input a,b;

  assign sout = a^b;
  assign cout = (a&b);

endmodule


module FA(sout,cout,a,b,cin);

  output sout,cout;
  input a,b,cin;

  assign sout =(a^b^cin);
  assign cout = ((a&b)|(a&cin)|(b&cin));

endmodule