Programmed (polling IO) requires busy-wait loop:
- CPU can't proceed with other computations
- CPU can't service other devices
Cpu must juggle many tasks concurrently.
Interrupt IO is an alternative to programmed IO. Basic idea - e.g. when key is pressed:
- keyboard IO inteface receives scancode from keyboard and stored in in data register.
- then the IO interface sends "interrupt request" signal to CPU.
- in response, CPU "interrupts" current task and saves its "context".
- CPU jumps to "interrupt service routing", which reads scancode and stores it in a buffer ("queue").
- when routine exits, CPU resumes original task by reloading "context".
- when app invokes routing to read next key, it is dequeued from buffer and returned.
The user can type ahead, because the kbd buffer has extra space.
in step 6, if a key hasn't been processed:
- it can return immediately with a special return value ("non blocking IO")
- it can busy wait until buffer non-empty (on single tasking OS)
- it can removeapp process from run queue until buffer non-empty (on multitasking OS)
Interrupt - a signal delivered to a CPU to tell it to suspend its current task (usually just temporarily) and invoke an interrupt service routine.
IRQ - Interrupt Request ISR - Interrupt Service Routine context switch - the process of saving and restoring state (e.g. CPU state), so that multiple processes (e.g. application vs. ISR) can share a resource (e.g. CPU).
The code is continually being interrupted:
- by IO intefaces
- by timers
- by other processes in the run queue
The processor needs an IRQ input. The signal might be asserted by an IO interface, such as a keyboard controller. It also needs a 1-bit IRQ mask which defaults to 1 on reset. Inside the CU, the IRQ signal is only propagated if the mask is 0. At the end of each fetch-execute cycle, the CU checks if IRQ is asserted. If not asserted, the next FE cycle is started. If asserted the CU performs the following, prior to starting the next FE cycle:
- setting the IRQ mask
- pushing PC on the stack
- pushing SR on the stack
- loading PC with the ISR start address
At the end of this sequence, the CU starts the next FE cycle. The first instruction of the ISR will be fetched.
At the end of the ISR, the interrupted code's CPU context must be restored:
- SR must be popped and restored
- PC must be popped and restored
- the IRQ mask must be cleared