axayjha · April 8, 2019 19:44
diff --git a/PIPO_R1.v b/PIPO_R1.v
 module PIPO_R1 (dout, din, ld, clk);
 	input [15:0] din;
 	input ld, clk;
 	output reg [15:0] dout;

 	always @(posedge clk)
                // if load signal is on, load new data
 		if (ld) dout <= din;
 endmodule
	module PIPO_R1 (dout, din, ld, clk);
	input [15:0] din;
	input ld, clk;
	output reg [15:0] dout;

	always @(posedge clk)
	// if load signal is on, load new data
	if (ld) dout <= din;
	endmodule