PIPO_R2.v

module PIPO_R2 (dout, din, ld, clr, clk);
	input [15:0] din;
	input ld, clr, clk;
	output reg [15:0] dout;

	always @(posedge clk)
                // if clear signal is on, set register value to 0
		if (clr) dout <= 16'b0;
                // else if load signal is on, load new data
		else if (ld) dout <= din;
endmodule