dff_async_reset.v

module dff_async_reset (
  input wire reset,
  input wire clock,
  input wire [7:0] input_data,
  output reg [7:0] output_data
);

always @(posedge clock or posedge reset)
  if (reset)
    output_data <= 0;
  else
    output_data <= input_data;

endmodule

run.sh

iverilog -o dff dff_async_reset.v test_dffar.v
vvp dff
gtkwave out.vcd

test_dffar.v

module test_dffar;

reg reset;
reg clk;
reg [7:0] input_data;
wire [7:0] output_data;

dff_async_reset dffar_inst(reset, clk, input_data, output_data);


always
  #10 clk = ~clk;


initial
begin
  reset = 0;
  clk = 0;
  input_data = 8'h00;

  #50;

  @(posedge clk)
  #0 input_data = 8'h55;

  #52 reset = 1;
  #4 reset = 0;

end

initial
begin
  #300 $finish;
end

initial
begin
  $dumpfile("out.vcd");
  $dumpvars(0, test_dffar);
end

endmodule