3-bit up counter for basys3

3-bit-counter.vhdl

-- barbarbar338
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity main_counter is
    Port (
        clk_in  : in  std_logic;  -- Basys3 100MHz clock
        reset   : in  std_logic;
        clk_out : out std_logic;
        count   : out std_logic_vector(2 downto 0)  -- 3-bit counter
    );
end main_counter;

architecture Behavioral of main_counter is
    -- Component declarations
    component freq_divider
        Port (
            clk_in  : in  std_logic;
            reset   : in  std_logic;
            clk_out : out std_logic
        );
    end component;

    component dff
        Port (
            clk   : in  std_logic;
            reset : in  std_logic;
            d     : in  std_logic;
            q     : out std_logic
        );
    end component;

    -- Internal signals
    signal slow_clk : std_logic;
    signal dff_q : std_logic_vector(2 downto 0);
    signal dff_d : std_logic_vector(2 downto 0); -- D inputs
begin
    -- Instantiate frequency divider
    -- Code: https://gist.github.com/barbarbar338/70742a493308aefb525fdb59a286a179
    u1: freq_divider
        port map (
            clk_in  => clk_in,
            reset   => reset,
            clk_out => slow_clk
        );

    -- Combinational logic for D inputs
    dff_d(0) <= not dff_q(0);
    dff_d(1) <= dff_q(1) xor dff_q(0);
    dff_d(2) <= dff_q(2) xor (dff_q(1) and dff_q(0));

    -- D Flip-Flops
    -- Code: https://gist.github.com/barbarbar338/29e05cf9aec846c85aadb8373ccc9f26
    dff0: dff port map (clk => slow_clk, reset => reset, d => dff_d(0), q => dff_q(0));
    dff1: dff port map (clk => slow_clk, reset => reset, d => dff_d(1), q => dff_q(1));
    dff2: dff port map (clk => slow_clk, reset => reset, d => dff_d(2), q => dff_q(2));

    -- Output assignment
    count <= dff_q;
    clk_out <= slow_clk;
end Behavioral;