D-flip-flop for Basys3 with reset - Positive-edge triggered

dff.vhdl

-- barbarbar338
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        d     : in  std_logic;
        q     : out std_logic
    );
end dff;

architecture Behavioral of dff is
begin
    process(clk, reset)
    begin
        if reset = '1' then
            q <= '0';
        elsif rising_edge(clk) then
            q <= d;
        end if;
    end process;
end Behavioral;