3-bit up counter for Basys3 using d-flip-flops - Full

basys3.xdc

## https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc

## Clock signal
set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk_in]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_in]

## LEDs
set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {count[0]}]
set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {count[1]}]
set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports {count[2]}]
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports clk_out]

##Buttons
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports reset]

## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

## SPI configuration mode options for QSPI boot, can be used for all designs
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

counter.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity main_counter is
    generic (
        DIVISOR : integer := 50000000  -- Default real FPGA value
    );
    Port (
        clk_in  : in  std_logic;  -- Basys3 100MHz clock
        reset   : in  std_logic;
        clk_out : out std_logic;
        count   : out std_logic_vector(2 downto 0)  -- 3-bit counter
    );
end main_counter;

architecture Behavioral of main_counter is
    -- Component declarations
    component freq_divider
        generic (
            DIVISOR : integer := 50000000
        );
        Port (
            clk_in  : in  std_logic;
            reset   : in  std_logic;
            clk_out : out std_logic
        );
    end component;

    component dff
        Port (
            clk   : in  std_logic;
            reset : in  std_logic;
            d     : in  std_logic;
            q     : out std_logic
        );
    end component;

    -- Internal signals
    signal slow_clk : std_logic;
    signal dff_q : std_logic_vector(2 downto 0);
    signal dff_d : std_logic_vector(2 downto 0); -- D inputs
begin
    -- Instantiate frequency divider
    -- Code: https://gist.github.com/barbarbar338/70742a493308aefb525fdb59a286a179
    u1: freq_divider
        generic map (
            DIVISOR => DIVISOR
        )
        port map (
            clk_in  => clk_in,
            reset   => reset,
            clk_out => slow_clk
        );

    -- Combinational logic for D inputs
    dff_d(0) <= not dff_q(0);
    dff_d(1) <= dff_q(1) xor dff_q(0);
    dff_d(2) <= dff_q(2) xor (dff_q(1) and dff_q(0));

    -- D Flip-Flops
    -- Code: https://gist.github.com/barbarbar338/29e05cf9aec846c85aadb8373ccc9f26
    dff0: dff port map (clk => slow_clk, reset => reset, d => dff_d(0), q => dff_q(0));
    dff1: dff port map (clk => slow_clk, reset => reset, d => dff_d(1), q => dff_q(1));
    dff2: dff port map (clk => slow_clk, reset => reset, d => dff_d(2), q => dff_q(2));

    -- Output assignment
    count <= dff_q;
    clk_out <= slow_clk;
end Behavioral;

dff.vhdl

-- barbarbar338
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        d     : in  std_logic;
        q     : out std_logic
    );
end dff;

architecture Behavioral of dff is
begin
    process(clk, reset)
    begin
        if reset = '1' then
            q <= '0';
        elsif rising_edge(clk) then
            q <= d;
        end if;
    end process;
end Behavioral;

freq_divider.vhdl

-- barbarbar338
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity freq_divider is
    generic (
        DIVISOR : integer := 50000000  -- Default for real hardware (50M)
    );
    port (
        clk_in  : in  std_logic;
        reset   : in  std_logic;
        clk_out : out std_logic
    );
end entity;

architecture Behavioral of freq_divider is
    signal counter : integer range 0 to DIVISOR := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            if reset = '1' then
                counter <= 0;
                clk_div <= '0';
            else
                if counter = DIVISOR then
                    clk_div <= not clk_div;
                    counter <= 0;
                else
                    counter <= counter + 1;
                end if;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end architecture;

tb_counter.vhdl

-- barbarbar338
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is
end entity;

architecture behavior of counter_tb is

    -- Component Declaration for the Unit Under Test (UUT)
    component counter
        generic (
            DIVISOR : integer := 50000000
        );
        port (
            clk_in  : in  std_logic;
            reset   : in  std_logic;
            clk_out : out std_logic;
            count   : out std_logic_vector(2 downto 0)
        );
    end component;

    -- Signals for connecting to the DUT
    signal clk_in  : std_logic := '0';
    signal reset   : std_logic := '0';
    signal clk_out : std_logic;
    signal count   : std_logic_vector(2 downto 0);

    -- Clock period definition
    constant clk_period : time := 10 ns;  -- Simulating 100 MHz clock

begin

    -- Instantiate the Unit Under Test (UUT)
    uut: counter
        generic map (
            DIVISOR => 5  -- Smaller value for simulation
        )
        port map (
            clk_in  => clk_in,
            reset   => reset,
            clk_out => clk_out,
            count   => count
        );

    -- Clock generation process
    clk_process : process
    begin
        while true loop
            clk_in <= '0';
            wait for clk_period/2;
            clk_in <= '1';
            wait for clk_period/2;
        end loop;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
        -- Initialize Inputs
        reset <= '1';
        wait for 20 ns;
        reset <= '0';

        -- Let it run for some time
        wait for 500 ns;

        -- Apply a reset again during operation
        reset <= '1';
        wait for 30 ns;
        reset <= '0';

        -- Observe after reset
        wait for 500 ns;

        -- Finish simulation
        wait;
    end process;

end architecture;