Clock divider for Basys3 - 100MegHz to 2Hz

clock_divider.vhdl

-- barbarbar338
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity freq_divider is
    Port (
        clk_in  : in  std_logic;  -- 100MHz clock input
        reset   : in  std_logic;
        clk_out : out std_logic   -- 2Hz clock output
    );
end freq_divider;

architecture Behavioral of freq_divider is
    constant DIVISOR : integer := 50_000_000; -- 100M / 2Hz / 2
    signal counter : integer range 0 to DIVISOR - 1 := 0;
    signal clk_reg : std_logic := '0';
begin
    process(clk_in, reset)
    begin
        if reset = '1' then
            counter <= 0;
            clk_reg <= '0';
        elsif rising_edge(clk_in) then
            if counter = DIVISOR - 1 then
                counter <= 0;
                clk_reg <= not clk_reg;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;
    
    clk_out <= clk_reg;
end Behavioral;