JK-flip-flop code for Basys3

jkflop.vhdl

-- barbarbar338
library ieee;
use ieee.std_logic_1164.all;

entity jk_flip_flop is
    port (
        clk : in std_logic;
        j   : in std_logic;
        k   : in std_logic;
        q   : out std_logic;
        qn  : out std_logic
    );
end entity;

architecture Behavioral of jk_flip_flop is
    signal q_int : std_logic := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if j = '0' and k = '0' then
                q_int <= q_int;       -- No change
            elsif j = '0' and k = '1' then
                q_int <= '0';         -- Reset
            elsif j = '1' and k = '0' then
                q_int <= '1';         -- Set
            elsif j = '1' and k = '1' then
                q_int <= not q_int;   -- Toggle
            end if;
        end if;
    end process;

    q  <= q_int;
    qn <= not q_int;
end architecture;