Created
July 8, 2020 20:38
-
-
Save bbrezillon/d5e527ab262f3799710f79db979c08cd to your computer and use it in GitHub Desktop.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| shader: MESA_SHADER_KERNEL | |
| local-size: 1, 1, 1 (variable) | |
| shared-size: 0 | |
| inputs: 4 | |
| outputs: 0 | |
| uniforms: 0 | |
| shared: 0 | |
| scratch: 288 | |
| decl_var ubo INTERP_MODE_NONE uint[5] kernel_inputs (0, 0, 0) | |
| decl_var ubo INTERP_MODE_NONE uint[11] kernel_work_properies (0, 0, 1) | |
| decl_var shader_in INTERP_MODE_NONE uint64_t @0 (0.x, 0, 0) | |
| decl_var shader_in INTERP_MODE_NONE float @1 (1.x, 8, 0) | |
| decl_var shader_in INTERP_MODE_NONE float @2 (2.x, 12, 0) | |
| decl_var shader_in INTERP_MODE_NONE float @3 (3.x, 16, 0) | |
| decl_function __wrapped_main_test (0 params) (entrypoint) | |
| impl __wrapped_main_test { | |
| block block_0: | |
| /* preds: */ | |
| vec1 1 ssa_3344 = load_const (false) | |
| vec1 32 ssa_3346 = load_const (0x00000000 /* 0.000000 */) | |
| vec4 32 ssa_1688 = intrinsic load_ubo_dxil (ssa_3346, ssa_3346) () | |
| vec1 32 ssa_3440 = mov ssa_1688.y | |
| vec4 32 ssa_1708 = intrinsic load_ubo_dxil (ssa_3346, ssa_3346) () | |
| vec1 1 ssa_3198 = load_const (true) | |
| vec1 32 ssa_3439 = mov ssa_1708.z | |
| vec4 32 ssa_1729 = intrinsic load_ubo_dxil (ssa_3346, ssa_3346) () | |
| vec1 32 ssa_3455 = mov ssa_1729.w | |
| vec1 32 ssa_3208 = load_const (0x00000001 /* 0.000000 */) | |
| vec4 32 ssa_1750 = intrinsic load_ubo_dxil (ssa_3346, ssa_3208) () | |
| vec1 32 ssa_3434 = mov ssa_1750.x | |
| vec1 32 ssa_20 = load_const (0x80000000 /* -0.000000 */) | |
| vec1 32 ssa_22 = load_const (0x007fffff /* 0.000000 */) | |
| vec1 32 ssa_31 = load_const (0x00000040 /* 0.000000 */) | |
| vec1 32 ssa_45 = load_const (0x7f800000 /* inf */) | |
| vec1 32 ssa_47 = load_const (0x00000017 /* 0.000000 */) | |
| vec1 32 ssa_48 = load_const (0x0000007f /* 0.000000 */) | |
| vec1 32 ssa_49 = load_const (0xffffff81 /* -nan */) | |
| vec1 32 ssa_92 = load_const (0x00800000 /* 0.000000 */) | |
| vec1 1 ssa_3495 = feq ssa_1708.z, ssa_1708.z | |
| /* succs: block_1 block_50 */ | |
| if ssa_3495 { | |
| block block_1: | |
| /* preds: block_0 */ | |
| vec1 1 ssa_3494 = feq ssa_1729.w, ssa_1729.w | |
| /* succs: block_2 block_48 */ | |
| if ssa_3494 { | |
| block block_2: | |
| /* preds: block_1 */ | |
| vec1 1 ssa_3493 = feq ssa_1750.x, ssa_1750.x | |
| /* succs: block_3 block_46 */ | |
| if ssa_3493 { | |
| block block_3: | |
| /* preds: block_2 */ | |
| vec1 32 ssa_168 = fabs ssa_1708.z | |
| vec1 1 ssa_3492 = ine ssa_168, ssa_45 | |
| /* succs: block_4 block_44 */ | |
| if ssa_3492 { | |
| block block_4: | |
| /* preds: block_3 */ | |
| vec1 32 ssa_178 = fabs ssa_1729.w | |
| vec1 1 ssa_3491 = ine ssa_178, ssa_45 | |
| /* succs: block_5 block_42 */ | |
| if ssa_3491 { | |
| block block_5: | |
| /* preds: block_4 */ | |
| vec1 32 ssa_188 = fabs ssa_1750.x | |
| vec1 1 ssa_3490 = ine ssa_188, ssa_45 | |
| /* succs: block_6 block_40 */ | |
| if ssa_3490 { | |
| block block_6: | |
| /* preds: block_5 */ | |
| vec1 32 ssa_209 = iand ssa_1708.z, ssa_45 | |
| vec1 1 ssa_210 = ieq ssa_209, ssa_3346 | |
| vec1 32 ssa_215 = iand ssa_1708.z, ssa_22 | |
| vec1 1 ssa_216 = ine ssa_215, ssa_3346 | |
| vec1 32 ssa_221 = iand ssa_1708.z, ssa_20 | |
| vec1 32 ssa_2416 = bcsel ssa_216, ssa_221, ssa_1708.z | |
| vec1 32 ssa_2418 = bcsel ssa_210, ssa_2416, ssa_1708.z | |
| vec1 32 ssa_250 = iand ssa_1729.w, ssa_45 | |
| vec1 1 ssa_251 = ieq ssa_250, ssa_3346 | |
| vec1 32 ssa_256 = iand ssa_1729.w, ssa_22 | |
| vec1 1 ssa_257 = ine ssa_256, ssa_3346 | |
| vec1 32 ssa_262 = iand ssa_1729.w, ssa_20 | |
| vec1 32 ssa_2420 = bcsel ssa_257, ssa_262, ssa_1729.w | |
| vec1 32 ssa_2422 = bcsel ssa_251, ssa_2420, ssa_1729.w | |
| vec1 32 ssa_291 = iand ssa_1750.x, ssa_45 | |
| vec1 1 ssa_292 = ieq ssa_291, ssa_3346 | |
| vec1 32 ssa_297 = iand ssa_1750.x, ssa_22 | |
| vec1 1 ssa_298 = ine ssa_297, ssa_3346 | |
| vec1 32 ssa_303 = iand ssa_1750.x, ssa_20 | |
| vec1 32 ssa_2424 = bcsel ssa_298, ssa_303, ssa_1750.x | |
| vec1 32 ssa_2426 = bcsel ssa_292, ssa_2424, ssa_1750.x | |
| vec1 1 ssa_318 = feq ssa_2426, ssa_3346 | |
| /* succs: block_7 block_8 */ | |
| if ssa_318 { | |
| block block_7: | |
| /* preds: block_6 */ | |
| vec1 32 ssa_323 = fmul ssa_2418, ssa_2422 | |
| /* succs: block_39 */ | |
| } else { | |
| block block_8: | |
| /* preds: block_6 */ | |
| vec1 1 ssa_329 = feq ssa_2418, ssa_3346 | |
| vec1 32 ssa_336 = iand ssa_2418, ssa_45 | |
| vec1 32 ssa_337 = ushr ssa_336, ssa_47 | |
| vec1 32 ssa_2341 = iadd ssa_337, ssa_49 | |
| vec1 32 ssa_2428 = bcsel ssa_329, ssa_3346, ssa_2341 | |
| vec1 32 ssa_3231 = load_const (0x0000000e /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2428, ssa_3231) () | |
| vec1 1 ssa_2338 = fne ssa_2422, ssa_3346 | |
| vec1 32 ssa_358 = iand ssa_2422, ssa_45 | |
| vec1 32 ssa_359 = ushr ssa_358, ssa_47 | |
| vec1 32 ssa_2337 = iadd ssa_359, ssa_49 | |
| vec1 32 ssa_2430 = bcsel ssa_2338, ssa_2337, ssa_3346 | |
| vec1 32 ssa_3235 = load_const (0x00000012 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2430, ssa_3235) () | |
| vec1 32 ssa_385 = iand ssa_2426, ssa_45 | |
| vec1 32 ssa_386 = ushr ssa_385, ssa_47 | |
| vec1 32 ssa_2334 = iadd ssa_386, ssa_49 | |
| vec1 32 ssa_3580 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3581 = isub ssa_3580, ssa_2334 | |
| vec1 32 ssa_3239 = load_const (0x00000016 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2334, ssa_3239) () | |
| vec1 1 ssa_2331 = fne ssa_2418, ssa_3346 | |
| vec1 32 ssa_407 = iand ssa_2418, ssa_22 | |
| vec1 32 ssa_408 = ior ssa_407, ssa_92 | |
| vec1 32 ssa_2434 = bcsel ssa_2331, ssa_408, ssa_3346 | |
| vec1 32 ssa_3240 = load_const (0x0000000c /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2434, ssa_3240) () | |
| vec1 32 ssa_3241 = load_const (0x0000000d /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_3346, ssa_3241) () | |
| vec1 1 ssa_427 = feq ssa_2422, ssa_3346 | |
| vec1 32 ssa_434 = iand ssa_2422, ssa_22 | |
| vec1 32 ssa_435 = ior ssa_434, ssa_92 | |
| vec1 32 ssa_2436 = bcsel ssa_427, ssa_3346, ssa_435 | |
| vec1 32 ssa_3242 = load_const (0x00000010 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2436, ssa_3242) () | |
| vec1 32 ssa_3243 = load_const (0x00000011 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_3346, ssa_3243) () | |
| vec1 1 ssa_2328 = fne ssa_2426, ssa_3346 | |
| vec1 32 ssa_456 = iand ssa_2426, ssa_22 | |
| vec1 32 ssa_457 = ior ssa_456, ssa_92 | |
| vec1 32 ssa_2438 = bcsel ssa_2328, ssa_457, ssa_3346 | |
| vec1 32 ssa_3244 = load_const (0x00000014 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2438, ssa_3244) () | |
| vec1 32 ssa_3245 = load_const (0x00000015 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_3346, ssa_3245) () | |
| vec1 32 ssa_477 = iand ssa_2418, ssa_20 | |
| vec1 32 ssa_3247 = load_const (0x0000000f /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_477, ssa_3247) () | |
| vec1 32 ssa_486 = iand ssa_2422, ssa_20 | |
| vec1 32 ssa_3249 = load_const (0x00000013 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_486, ssa_3249) () | |
| vec1 32 ssa_495 = iand ssa_2426, ssa_20 | |
| intrinsic store_scratch_dxil (ssa_495, ssa_47) () | |
| vec1 32 ssa_513 = ixor ssa_477, ssa_486 | |
| vec1 32 ssa_3254 = load_const (0x0000001b /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_513, ssa_3254) () | |
| vec1 32 ssa_3168 = load_const (0x0000ffff /* 0.000000 */) | |
| vec1 32 ssa_3169 = iand ssa_2434, ssa_3168 | |
| vec1 32 ssa_3170 = iand ssa_2436, ssa_3168 | |
| vec1 32 ssa_3171 = ushr ssa_2434, ssa_3242 | |
| vec1 32 ssa_3172 = ushr ssa_2436, ssa_3242 | |
| vec1 32 ssa_3173 = imul ssa_3169, ssa_3170 | |
| vec1 32 ssa_3174 = imul ssa_3169, ssa_3172 | |
| vec1 32 ssa_3175 = imul ssa_3171, ssa_3170 | |
| vec1 32 ssa_3176 = imul ssa_3171, ssa_3172 | |
| vec1 32 ssa_3177 = ishl ssa_3174, ssa_3242 | |
| vec1 32 ssa_3415 = iadd ssa_3173, ssa_3177 | |
| vec1 1 ssa_3416 = ult ssa_3415, ssa_3173 | |
| vec1 32 ssa_3417 = b2i32 ssa_3416 | |
| vec1 32 ssa_3179 = iand ssa_3417, ssa_3208 | |
| vec1 32 ssa_3180 = iadd ssa_3176, ssa_3179 | |
| vec1 32 ssa_3182 = ushr ssa_3174, ssa_3242 | |
| vec1 32 ssa_3183 = iadd ssa_3180, ssa_3182 | |
| vec1 32 ssa_3184 = ishl ssa_3175, ssa_3242 | |
| vec1 32 ssa_3412 = iadd ssa_3415, ssa_3184 | |
| vec1 1 ssa_3413 = ult ssa_3412, ssa_3415 | |
| vec1 32 ssa_3414 = b2i32 ssa_3413 | |
| vec1 32 ssa_3186 = iand ssa_3414, ssa_3208 | |
| vec1 32 ssa_3187 = iadd ssa_3183, ssa_3186 | |
| vec1 32 ssa_3189 = ushr ssa_3175, ssa_3242 | |
| vec1 32 ssa_3190 = iadd ssa_3187, ssa_3189 | |
| vec1 32 ssa_2529 = imul ssa_2434, ssa_2436 | |
| vec1 32 ssa_2537 = ishl ssa_2529, ssa_3231 | |
| vec1 32 ssa_2538 = ishl ssa_3190, ssa_3231 | |
| vec1 32 ssa_2539 = ushr ssa_2529, ssa_3235 | |
| vec1 32 ssa_2540 = ior ssa_2538, ssa_2539 | |
| vec1 32 ssa_3260 = load_const (0x00000018 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2537, ssa_3260) () | |
| vec1 32 ssa_3261 = load_const (0x00000019 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2540, ssa_3261) () | |
| vec1 32 ssa_2319 = ior ssa_2537, ssa_2540 | |
| vec1 1 ssa_2321 = ine ssa_2319, ssa_3346 | |
| vec1 32 ssa_558 = iadd ssa_2428, ssa_2430 | |
| vec1 32 ssa_2440 = bcsel ssa_2321, ssa_558, ssa_3346 | |
| vec1 32 ssa_3263 = load_const (0x0000001a /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2440, ssa_3263) () | |
| vec1 1 ssa_580 = ieq ssa_2440, ssa_3346 | |
| vec1 1 ssa_2443 = bcsel ssa_580, ssa_2321, ssa_3198 | |
| /* succs: block_9 block_37 */ | |
| if ssa_2443 { | |
| block block_9: | |
| /* preds: block_8 */ | |
| vec1 32 ssa_3579 = isub ssa_2440, ssa_2334 | |
| vec1 32 ssa_3594 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3595 = isub ssa_3594, ssa_3579 | |
| vec1 32 ssa_3578 = imax ssa_3579, ssa_3595 | |
| vec1 32 ssa_3573 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3574 = isub ssa_3573, ssa_3579 | |
| vec1 32 ssa_3264 = load_const (0x00000025 /* 0.000000 */) | |
| vec1 32 ssa_3266 = load_const (0x00000005 /* 0.000000 */) | |
| vec1 32 ssa_2577 = ishl ssa_2438, ssa_3266 | |
| intrinsic store_scratch_dxil (ssa_3346, ssa_3244) () | |
| intrinsic store_scratch_dxil (ssa_2577, ssa_3245) () | |
| vec1 32 ssa_3269 = load_const (0x0000003f /* 0.000000 */) | |
| vec1 32 ssa_2606 = iand ssa_3578, ssa_3269 | |
| vec1 32 ssa_2611 = load_const (0xffffffe0 /* -nan */) | |
| vec1 32 ssa_2612 = iadd ssa_2606, ssa_2611 | |
| vec1 32 ssa_3592 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3593 = isub ssa_3592, ssa_2612 | |
| vec1 32 ssa_3576 = imax ssa_2612, ssa_3593 | |
| vec1 32 ssa_2614 = ishl ssa_3208, ssa_2606 | |
| vec1 32 ssa_2616 = ushr ssa_3208, ssa_3576 | |
| vec1 32 ssa_2620 = ishl ssa_3208, ssa_3576 | |
| vec1 32 ssa_2622 = load_const (0x00000020 /* 0.000000 */) | |
| vec1 1 ssa_2623 = uge ssa_2606, ssa_2622 | |
| vec1 32 ssa_2632 = bcsel ssa_2623, ssa_2620, ssa_2616 | |
| vec1 32 ssa_2633 = bcsel ssa_2623, ssa_3346, ssa_2614 | |
| vec1 1 ssa_2626 = ieq ssa_2606, ssa_3346 | |
| vec1 32 ssa_2640 = bcsel ssa_2626, ssa_3208, ssa_2633 | |
| vec1 32 ssa_3286 = load_const (0xffffffff /* -nan */) | |
| vec1 32 ssa_2658 = iadd ssa_2640, ssa_3286 | |
| vec1 1 ssa_2659 = ult ssa_2658, ssa_2640 | |
| vec1 32 ssa_2660 = b2i32 ssa_2659 | |
| vec1 32 ssa_3485 = iadd ssa_2632, ssa_3286 | |
| vec1 32 ssa_3486 = bcsel ssa_2626, ssa_3286, ssa_3485 | |
| vec1 32 ssa_2662 = iadd ssa_2660, ssa_3486 | |
| vec1 1 ssa_2305 = ige ssa_3346, ssa_3579 | |
| /* succs: block_10 block_11 */ | |
| if ssa_2305 { | |
| block block_10: | |
| /* preds: block_9 */ | |
| vec1 1 ssa_2302 = ilt ssa_3574, ssa_31 | |
| vec1 32 ssa_2668 = iand ssa_2540, ssa_2662 | |
| vec1 32 ssa_2669 = iand ssa_2537, ssa_2658 | |
| vec1 32 ssa_2446 = bcsel ssa_2302, ssa_2669, ssa_2537 | |
| vec1 32 ssa_2447 = bcsel ssa_2302, ssa_2668, ssa_2540 | |
| vec1 1 ssa_671 = ige ssa_3574, ssa_31 | |
| vec1 32 ssa_2678 = iand ssa_3574, ssa_3269 | |
| vec1 32 ssa_2684 = iadd ssa_2678, ssa_2611 | |
| vec1 32 ssa_3590 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3591 = isub ssa_3590, ssa_2684 | |
| vec1 32 ssa_3572 = imax ssa_2684, ssa_3591 | |
| vec1 32 ssa_2686 = ushr ssa_2537, ssa_2678 | |
| vec1 32 ssa_2687 = ushr ssa_2540, ssa_2678 | |
| vec1 32 ssa_2688 = ishl ssa_2540, ssa_3572 | |
| vec1 32 ssa_2689 = ior ssa_2686, ssa_2688 | |
| vec1 32 ssa_2692 = ushr ssa_2540, ssa_3572 | |
| vec1 1 ssa_2695 = uge ssa_2678, ssa_2622 | |
| vec1 32 ssa_2704 = bcsel ssa_2695, ssa_3346, ssa_2687 | |
| vec1 32 ssa_2705 = bcsel ssa_2695, ssa_2692, ssa_2689 | |
| vec1 1 ssa_2698 = ieq ssa_2678, ssa_3346 | |
| vec1 32 ssa_2711 = bcsel ssa_2698, ssa_2540, ssa_2704 | |
| vec1 32 ssa_2712 = bcsel ssa_2698, ssa_2537, ssa_2705 | |
| vec1 32 ssa_2449 = bcsel ssa_671, ssa_3346, ssa_2712 | |
| vec1 32 ssa_2450 = bcsel ssa_671, ssa_3346, ssa_2711 | |
| intrinsic store_scratch_dxil (ssa_2449, ssa_3260) () | |
| intrinsic store_scratch_dxil (ssa_2450, ssa_3261) () | |
| /* succs: block_12 */ | |
| } else { | |
| block block_11: | |
| /* preds: block_9 */ | |
| vec1 1 ssa_704 = ige ssa_3579, ssa_31 | |
| vec1 32 ssa_2718 = iand ssa_2577, ssa_2662 | |
| vec1 32 ssa_2453 = bcsel ssa_704, ssa_2577, ssa_2718 | |
| vec1 1 ssa_2296 = ilt ssa_3579, ssa_31 | |
| vec1 32 ssa_2728 = iand ssa_3579, ssa_3269 | |
| vec1 32 ssa_2734 = iadd ssa_2728, ssa_2611 | |
| vec1 32 ssa_3588 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3589 = isub ssa_3588, ssa_2734 | |
| vec1 32 ssa_3570 = imax ssa_2734, ssa_3589 | |
| vec1 32 ssa_2737 = ushr ssa_2577, ssa_2728 | |
| vec1 32 ssa_2738 = ishl ssa_2577, ssa_3570 | |
| vec1 32 ssa_2742 = ushr ssa_2577, ssa_3570 | |
| vec1 1 ssa_2745 = uge ssa_2728, ssa_2622 | |
| vec1 32 ssa_2754 = bcsel ssa_2745, ssa_3346, ssa_2737 | |
| vec1 32 ssa_2755 = bcsel ssa_2745, ssa_2742, ssa_2738 | |
| vec1 1 ssa_2748 = ieq ssa_2728, ssa_3346 | |
| vec1 32 ssa_2761 = bcsel ssa_2748, ssa_2577, ssa_2754 | |
| vec1 32 ssa_2762 = bcsel ssa_2748, ssa_3346, ssa_2755 | |
| vec1 32 ssa_2455 = bcsel ssa_2296, ssa_2762, ssa_3346 | |
| vec1 32 ssa_2456 = bcsel ssa_2296, ssa_2761, ssa_3346 | |
| intrinsic store_scratch_dxil (ssa_2455, ssa_3244) () | |
| intrinsic store_scratch_dxil (ssa_2456, ssa_3245) () | |
| /* succs: block_12 */ | |
| } | |
| block block_12: | |
| /* preds: block_10 block_11 */ | |
| vec1 32 ssa_2412 = phi block_10: ssa_2446, block_11: ssa_3346 | |
| vec1 32 ssa_2413 = phi block_10: ssa_2447, block_11: ssa_2453 | |
| intrinsic store_scratch_dxil (ssa_513, ssa_3264) () | |
| vec1 32 ssa_789 = imax ssa_2440, ssa_2334 | |
| vec1 32 ssa_3296 = load_const (0x00000024 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_789, ssa_3296) () | |
| vec1 1 ssa_2292 = ine ssa_495, ssa_513 | |
| /* succs: block_13 block_14 */ | |
| if ssa_2292 { | |
| block block_13: | |
| /* preds: block_12 */ | |
| vec1 32 ssa_1950 = intrinsic load_scratch_dxil (ssa_3260) () | |
| vec1 32 ssa_1953 = intrinsic load_scratch_dxil (ssa_3261) () | |
| vec1 32 ssa_1964 = intrinsic load_scratch_dxil (ssa_3244) () | |
| vec1 32 ssa_1967 = intrinsic load_scratch_dxil (ssa_3245) () | |
| vec1 32 ssa_3567 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3568 = isub ssa_3567, ssa_1964 | |
| vec1 1 ssa_2771 = ult ssa_3346, ssa_1964 | |
| vec1 32 ssa_2772 = b2i32 ssa_2771 | |
| vec1 32 ssa_3565 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3566 = isub ssa_3565, ssa_2772 | |
| vec1 32 ssa_3563 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3564 = isub ssa_3563, ssa_1967 | |
| vec1 32 ssa_3562 = isub ssa_3564, ssa_2772 | |
| vec1 32 ssa_3561 = isub ssa_1950, ssa_1964 | |
| vec1 1 ssa_2782 = ult ssa_3561, ssa_1950 | |
| vec1 32 ssa_2783 = b2i32 ssa_2782 | |
| vec1 32 ssa_2784 = iadd ssa_1953, ssa_3562 | |
| vec1 32 ssa_2785 = iadd ssa_2783, ssa_2784 | |
| vec1 32 ssa_2285 = ior ssa_2412, ssa_2413 | |
| vec1 1 ssa_2287 = ine ssa_2285, ssa_3346 | |
| vec1 1 ssa_840 = ilt ssa_2334, ssa_2440 | |
| vec1 1 ssa_2467 = iand ssa_2287, ssa_840 | |
| vec1 32 ssa_848 = bcsel ssa_2467, ssa_3208, ssa_3346 | |
| vec1 32 ssa_3559 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3560 = isub ssa_3559, ssa_848 | |
| vec1 32 ssa_2787 = load_const (0x0000001f /* 0.000000 */) | |
| vec1 32 ssa_2788 = ishr ssa_848, ssa_2787 | |
| vec1 32 ssa_3555 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3556 = isub ssa_3555, ssa_2788 | |
| vec1 32 ssa_2797 = b2i32 ssa_2467 | |
| vec1 32 ssa_3557 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3558 = isub ssa_3557, ssa_2797 | |
| vec1 32 ssa_3554 = isub ssa_3556, ssa_2797 | |
| vec1 32 ssa_3553 = isub ssa_3561, ssa_848 | |
| vec1 1 ssa_2807 = ult ssa_3553, ssa_3561 | |
| vec1 32 ssa_2808 = b2i32 ssa_2807 | |
| vec1 32 ssa_2809 = iadd ssa_2785, ssa_3554 | |
| vec1 32 ssa_2810 = iadd ssa_2808, ssa_2809 | |
| vec1 32 ssa_3301 = load_const (0x00000022 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_3553, ssa_3301) () | |
| vec1 32 ssa_3302 = load_const (0x00000023 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2810, ssa_3302) () | |
| /* succs: block_15 */ | |
| } else { | |
| block block_14: | |
| /* preds: block_12 */ | |
| vec1 32 ssa_1992 = intrinsic load_scratch_dxil (ssa_3260) () | |
| vec1 32 ssa_1995 = intrinsic load_scratch_dxil (ssa_3261) () | |
| vec1 32 ssa_2006 = intrinsic load_scratch_dxil (ssa_3244) () | |
| vec1 32 ssa_2009 = intrinsic load_scratch_dxil (ssa_3245) () | |
| vec1 32 ssa_2816 = iadd ssa_1992, ssa_2006 | |
| vec1 1 ssa_2817 = ult ssa_2816, ssa_1992 | |
| vec1 32 ssa_2818 = b2i32 ssa_2817 | |
| vec1 32 ssa_2819 = iadd ssa_1995, ssa_2009 | |
| vec1 32 ssa_2820 = iadd ssa_2818, ssa_2819 | |
| vec1 32 ssa_3303 = load_const (0x00000022 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2816, ssa_3303) () | |
| vec1 32 ssa_3304 = load_const (0x00000023 /* 0.000000 */) | |
| intrinsic store_scratch_dxil (ssa_2820, ssa_3304) () | |
| /* succs: block_15 */ | |
| } | |
| block block_15: | |
| /* preds: block_13 block_14 */ | |
| vec1 32 ssa_3305 = load_const (0x00000022 /* 0.000000 */) | |
| vec1 32 ssa_2034 = intrinsic load_scratch_dxil (ssa_3305) () | |
| vec1 32 ssa_3306 = load_const (0x00000023 /* 0.000000 */) | |
| vec1 32 ssa_2037 = intrinsic load_scratch_dxil (ssa_3306) () | |
| vec1 32 ssa_3308 = load_const (0x7fffffff /* nan */) | |
| vec1 1 ssa_2826 = ult ssa_3286, ssa_2034 | |
| vec1 1 ssa_2827 = ieq ssa_3308, ssa_2037 | |
| vec1 1 ssa_2828 = iand ssa_2827, ssa_2826 | |
| vec1 1 ssa_2829 = ult ssa_3308, ssa_2037 | |
| vec1 1 ssa_2830 = ior ssa_2829, ssa_2828 | |
| /* succs: block_16 block_17 */ | |
| if ssa_2830 { | |
| block block_16: | |
| /* preds: block_15 */ | |
| vec1 32 ssa_3551 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3552 = isub ssa_3551, ssa_2034 | |
| vec1 1 ssa_2837 = ult ssa_3346, ssa_2034 | |
| vec1 32 ssa_2838 = b2i32 ssa_2837 | |
| vec1 32 ssa_3549 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3550 = isub ssa_3549, ssa_2838 | |
| vec1 32 ssa_3547 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3548 = isub ssa_3547, ssa_2037 | |
| vec1 32 ssa_3546 = isub ssa_3548, ssa_2838 | |
| intrinsic store_scratch_dxil (ssa_3552, ssa_3305) () | |
| intrinsic store_scratch_dxil (ssa_3546, ssa_3306) () | |
| vec1 32 ssa_907 = ixor ssa_513, ssa_20 | |
| intrinsic store_scratch_dxil (ssa_907, ssa_3264) () | |
| /* succs: block_18 */ | |
| } else { | |
| block block_17: | |
| /* preds: block_15 */ | |
| /* succs: block_18 */ | |
| } | |
| block block_18: | |
| /* preds: block_16 block_17 */ | |
| vec1 32 ssa_2070 = intrinsic load_scratch_dxil (ssa_3305) () | |
| vec1 32 ssa_2073 = intrinsic load_scratch_dxil (ssa_3306) () | |
| vec1 32 ssa_2845 = ufind_msb ssa_2070 | |
| vec1 32 ssa_2846 = ufind_msb ssa_2073 | |
| vec1 1 ssa_2848 = ine ssa_2073, ssa_3346 | |
| vec1 32 ssa_2850 = iadd ssa_2622, ssa_2846 | |
| vec1 32 ssa_2851 = bcsel ssa_2848, ssa_2850, ssa_2845 | |
| vec1 32 ssa_3544 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3545 = isub ssa_3544, ssa_2851 | |
| vec1 32 ssa_3543 = isub ssa_3269, ssa_2851 | |
| vec1 32 ssa_3541 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3542 = isub ssa_3541, ssa_3543 | |
| vec1 32 ssa_3460 = load_const (0x00000003 /* 0.000000 */) | |
| vec1 32 ssa_3540 = isub ssa_3460, ssa_3543 | |
| vec1 32 ssa_3538 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3539 = isub ssa_3538, ssa_3540 | |
| vec1 32 ssa_938 = iadd ssa_789, ssa_3540 | |
| intrinsic store_scratch_dxil (ssa_938, ssa_3296) () | |
| vec1 1 ssa_941 = ilt ssa_3540, ssa_3346 | |
| /* succs: block_19 block_20 */ | |
| if ssa_941 { | |
| block block_19: | |
| /* preds: block_18 */ | |
| vec1 32 ssa_2884 = iand ssa_3539, ssa_3269 | |
| vec1 32 ssa_2890 = iadd ssa_2884, ssa_2611 | |
| vec1 32 ssa_3586 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3587 = isub ssa_3586, ssa_2890 | |
| vec1 32 ssa_3537 = imax ssa_2890, ssa_3587 | |
| vec1 32 ssa_2892 = ishl ssa_2070, ssa_2884 | |
| vec1 32 ssa_2893 = ishl ssa_2073, ssa_2884 | |
| vec1 32 ssa_2894 = ushr ssa_2070, ssa_3537 | |
| vec1 32 ssa_2895 = ior ssa_2893, ssa_2894 | |
| vec1 32 ssa_2898 = ishl ssa_2070, ssa_3537 | |
| vec1 1 ssa_2901 = uge ssa_2884, ssa_2622 | |
| vec1 32 ssa_2910 = bcsel ssa_2901, ssa_2898, ssa_2895 | |
| vec1 32 ssa_2911 = bcsel ssa_2901, ssa_3346, ssa_2892 | |
| vec1 1 ssa_2904 = ieq ssa_2884, ssa_3346 | |
| vec1 32 ssa_2917 = bcsel ssa_2904, ssa_2073, ssa_2910 | |
| vec1 32 ssa_2918 = bcsel ssa_2904, ssa_2070, ssa_2911 | |
| intrinsic store_scratch_dxil (ssa_2918, ssa_3305) () | |
| intrinsic store_scratch_dxil (ssa_2917, ssa_3306) () | |
| /* succs: block_21 */ | |
| } else { | |
| block block_20: | |
| /* preds: block_18 */ | |
| /* succs: block_21 */ | |
| } | |
| block block_21: | |
| /* preds: block_19 block_20 */ | |
| vec1 32 ssa_1380 = phi block_19: ssa_3346, block_20: ssa_3540 | |
| vec1 32 ssa_2920 = load_const (0x0000001f /* 0.000000 */) | |
| vec1 32 ssa_2927 = iadd ssa_3264, ssa_1380 | |
| vec1 32 ssa_2938 = iand ssa_2927, ssa_3269 | |
| vec1 32 ssa_2944 = iadd ssa_2938, ssa_2611 | |
| vec1 32 ssa_3584 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3585 = isub ssa_3584, ssa_2944 | |
| vec1 32 ssa_3535 = imax ssa_2944, ssa_3585 | |
| vec1 32 ssa_2946 = ishl ssa_3208, ssa_2938 | |
| vec1 32 ssa_2948 = ushr ssa_3208, ssa_3535 | |
| vec1 32 ssa_2952 = ishl ssa_3208, ssa_3535 | |
| vec1 1 ssa_2955 = uge ssa_2938, ssa_2622 | |
| vec1 32 ssa_2964 = bcsel ssa_2955, ssa_2952, ssa_2948 | |
| vec1 32 ssa_2965 = bcsel ssa_2955, ssa_3346, ssa_2946 | |
| vec1 1 ssa_2958 = ieq ssa_2938, ssa_3346 | |
| vec1 32 ssa_2971 = bcsel ssa_2958, ssa_3346, ssa_2964 | |
| vec1 32 ssa_2972 = bcsel ssa_2958, ssa_3208, ssa_2965 | |
| vec1 32 ssa_2978 = iadd ssa_2972, ssa_3286 | |
| vec1 1 ssa_2979 = ult ssa_2978, ssa_2972 | |
| vec1 32 ssa_2980 = b2i32 ssa_2979 | |
| vec1 32 ssa_2981 = iadd ssa_2971, ssa_3286 | |
| vec1 32 ssa_2982 = iadd ssa_2980, ssa_2981 | |
| vec1 32 ssa_2106 = intrinsic load_scratch_dxil (ssa_3305) () | |
| vec1 32 ssa_2109 = intrinsic load_scratch_dxil (ssa_3306) () | |
| vec1 32 ssa_2988 = iand ssa_2109, ssa_2982 | |
| vec1 32 ssa_2989 = iand ssa_2106, ssa_2978 | |
| vec1 32 ssa_2257 = ior ssa_2412, ssa_2413 | |
| vec1 1 ssa_2259 = ine ssa_2257, ssa_3346 | |
| vec1 32 ssa_983 = bcsel ssa_2259, ssa_3208, ssa_3346 | |
| vec1 32 ssa_2992 = ishr ssa_983, ssa_2920 | |
| vec1 32 ssa_2998 = ior ssa_2988, ssa_2992 | |
| vec1 32 ssa_2999 = ior ssa_2989, ssa_983 | |
| vec1 32 ssa_3005 = iand ssa_2109, ssa_2971 | |
| vec1 32 ssa_3006 = iand ssa_2106, ssa_2972 | |
| vec1 32 ssa_3012 = iadd ssa_3305, ssa_1380 | |
| vec1 32 ssa_3023 = iand ssa_3012, ssa_3269 | |
| vec1 32 ssa_3331 = load_const (0x00000004 /* 0.000000 */) | |
| vec1 32 ssa_3029 = iadd ssa_3023, ssa_2611 | |
| vec1 32 ssa_3582 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_3583 = isub ssa_3582, ssa_3029 | |
| vec1 32 ssa_3533 = imax ssa_3029, ssa_3583 | |
| vec1 32 ssa_3031 = ishl ssa_3331, ssa_3023 | |
| vec1 32 ssa_3033 = ushr ssa_3331, ssa_3533 | |
| vec1 32 ssa_3037 = ishl ssa_3331, ssa_3533 | |
| vec1 1 ssa_3040 = uge ssa_3023, ssa_2622 | |
| vec1 32 ssa_3049 = bcsel ssa_3040, ssa_3037, ssa_3033 | |
| vec1 32 ssa_3050 = bcsel ssa_3040, ssa_3346, ssa_3031 | |
| vec1 1 ssa_3043 = ieq ssa_3023, ssa_3346 | |
| vec1 32 ssa_3056 = bcsel ssa_3043, ssa_3346, ssa_3049 | |
| vec1 32 ssa_3057 = bcsel ssa_3043, ssa_3331, ssa_3050 | |
| vec1 1 ssa_3067 = ult ssa_3057, ssa_2999 | |
| vec1 1 ssa_3068 = ieq ssa_3056, ssa_2998 | |
| vec1 1 ssa_3069 = iand ssa_3068, ssa_3067 | |
| vec1 1 ssa_3070 = ult ssa_3056, ssa_2998 | |
| vec1 1 ssa_3071 = ior ssa_3070, ssa_3069 | |
| vec1 1 ssa_3077 = ieq ssa_2999, ssa_3057 | |
| vec1 1 ssa_3079 = iand ssa_3068, ssa_3077 | |
| vec1 32 ssa_2251 = ior ssa_3006, ssa_3005 | |
| vec1 1 ssa_2253 = ine ssa_2251, ssa_3346 | |
| vec1 1 ssa_2465 = iand ssa_3079, ssa_2253 | |
| vec1 1 ssa_3482 = ior ssa_3071, ssa_2465 | |
| /* succs: block_22 block_23 */ | |
| if ssa_3482 { | |
| block block_22: | |
| /* preds: block_21 */ | |
| vec1 32 ssa_3084 = iadd ssa_2106, ssa_2972 | |
| vec1 1 ssa_3085 = ult ssa_3084, ssa_2106 | |
| vec1 32 ssa_3086 = b2i32 ssa_3085 | |
| vec1 32 ssa_3087 = iadd ssa_2109, ssa_2971 | |
| vec1 32 ssa_3088 = iadd ssa_3086, ssa_3087 | |
| intrinsic store_scratch_dxil (ssa_3084, ssa_3305) () | |
| intrinsic store_scratch_dxil (ssa_3088, ssa_3306) () | |
| /* succs: block_24 */ | |
| } else { | |
| block block_23: | |
| /* preds: block_21 */ | |
| /* succs: block_24 */ | |
| } | |
| block block_24: | |
| /* preds: block_22 block_23 */ | |
| vec1 32 ssa_2134 = intrinsic load_scratch_dxil (ssa_3305) () | |
| vec1 32 ssa_2137 = intrinsic load_scratch_dxil (ssa_3306) () | |
| vec1 32 ssa_3095 = ushr ssa_2134, ssa_2938 | |
| vec1 32 ssa_3096 = ushr ssa_2137, ssa_2938 | |
| vec1 32 ssa_3097 = ishl ssa_2137, ssa_3535 | |
| vec1 32 ssa_3098 = ior ssa_3095, ssa_3097 | |
| vec1 32 ssa_3101 = ushr ssa_2137, ssa_3535 | |
| vec1 32 ssa_3113 = bcsel ssa_2955, ssa_3346, ssa_3096 | |
| vec1 32 ssa_3114 = bcsel ssa_2955, ssa_3101, ssa_3098 | |
| vec1 32 ssa_3120 = bcsel ssa_2958, ssa_2137, ssa_3113 | |
| vec1 32 ssa_3121 = bcsel ssa_2958, ssa_2134, ssa_3114 | |
| intrinsic store_scratch_dxil (ssa_3121, ssa_3305) () | |
| intrinsic store_scratch_dxil (ssa_3120, ssa_3306) () | |
| vec1 32 ssa_3335 = load_const (0x00ffffff /* 0.000000 */) | |
| vec1 1 ssa_3127 = ult ssa_3335, ssa_3121 | |
| vec1 1 ssa_3128 = ieq ssa_3346, ssa_3120 | |
| vec1 1 ssa_3129 = iand ssa_3128, ssa_3127 | |
| vec1 1 ssa_3130 = ult ssa_3346, ssa_3120 | |
| vec1 1 ssa_3131 = ior ssa_3130, ssa_3129 | |
| /* succs: block_25 block_26 */ | |
| if ssa_3131 { | |
| block block_25: | |
| /* preds: block_24 */ | |
| vec1 32 ssa_1086 = iadd ssa_938, ssa_3208 | |
| intrinsic store_scratch_dxil (ssa_1086, ssa_3296) () | |
| vec1 32 ssa_3138 = ushr ssa_3121, ssa_3208 | |
| vec1 32 ssa_3139 = ushr ssa_3120, ssa_3208 | |
| vec1 32 ssa_3140 = ishl ssa_3120, ssa_2920 | |
| vec1 32 ssa_3141 = ior ssa_3138, ssa_3140 | |
| intrinsic store_scratch_dxil (ssa_3141, ssa_3305) () | |
| intrinsic store_scratch_dxil (ssa_3139, ssa_3306) () | |
| /* succs: block_27 */ | |
| } else { | |
| block block_26: | |
| /* preds: block_24 */ | |
| /* succs: block_27 */ | |
| } | |
| block block_27: | |
| /* preds: block_25 block_26 */ | |
| vec1 32 ssa_2184 = intrinsic load_scratch_dxil (ssa_3305) () | |
| vec1 32 ssa_2187 = intrinsic load_scratch_dxil (ssa_3306) () | |
| vec1 32 ssa_2240 = ior ssa_2184, ssa_2187 | |
| vec1 1 ssa_3377 = ine ssa_2240, ssa_3346 | |
| /* succs: block_28 block_35 */ | |
| if ssa_3377 { | |
| block block_28: | |
| /* preds: block_27 */ | |
| vec1 32 ssa_2198 = intrinsic load_scratch_dxil (ssa_3296) () | |
| vec1 1 ssa_2236 = ige ssa_48, ssa_2198 | |
| /* succs: block_29 block_33 */ | |
| if ssa_2236 { | |
| block block_29: | |
| /* preds: block_28 */ | |
| vec1 1 ssa_1123 = ige ssa_49, ssa_2198 | |
| /* succs: block_30 block_31 */ | |
| if ssa_1123 { | |
| block block_30: | |
| /* preds: block_29 */ | |
| vec1 32 ssa_2206 = intrinsic load_scratch_dxil (ssa_3264) () | |
| /* succs: block_32 */ | |
| } else { | |
| block block_31: | |
| /* preds: block_29 */ | |
| vec1 32 ssa_2214 = intrinsic load_scratch_dxil (ssa_3264) () | |
| vec1 32 ssa_2231 = ishl ssa_2198, ssa_47 | |
| vec1 32 ssa_3342 = load_const (0x3f800000 /* 1.000000 */) | |
| vec1 32 ssa_2233 = iadd ssa_2231, ssa_3342 | |
| vec1 32 ssa_1148 = ior ssa_2214, ssa_2233 | |
| vec1 32 ssa_1156 = iand ssa_2184, ssa_22 | |
| vec1 32 ssa_1157 = ior ssa_1148, ssa_1156 | |
| /* succs: block_32 */ | |
| } | |
| block block_32: | |
| /* preds: block_30 block_31 */ | |
| vec1 32 ssa_1340 = phi block_30: ssa_2206, block_31: ssa_1157 | |
| /* succs: block_34 */ | |
| } else { | |
| block block_33: | |
| /* preds: block_28 */ | |
| vec1 32 ssa_2222 = intrinsic load_scratch_dxil (ssa_3264) () | |
| vec1 32 ssa_1168 = ior ssa_45, ssa_2222 | |
| /* succs: block_34 */ | |
| } | |
| block block_34: | |
| /* preds: block_32 block_33 */ | |
| vec1 32 ssa_1339 = phi block_32: ssa_1340, block_33: ssa_1168 | |
| /* succs: block_36 */ | |
| } else { | |
| block block_35: | |
| /* preds: block_27 */ | |
| /* succs: block_36 */ | |
| } | |
| block block_36: | |
| /* preds: block_34 block_35 */ | |
| vec1 32 ssa_1338 = phi block_35: ssa_3346, block_34: ssa_1339 | |
| /* succs: block_38 */ | |
| } else { | |
| block block_37: | |
| /* preds: block_8 */ | |
| /* succs: block_38 */ | |
| } | |
| block block_38: | |
| /* preds: block_36 block_37 */ | |
| vec1 32 ssa_1329 = phi block_36: ssa_1338, block_37: ssa_2426 | |
| /* succs: block_39 */ | |
| } | |
| block block_39: | |
| /* preds: block_7 block_38 */ | |
| vec1 32 ssa_1321 = phi block_7: ssa_323, block_38: ssa_1329 | |
| /* succs: block_41 */ | |
| } else { | |
| block block_40: | |
| /* preds: block_5 */ | |
| /* succs: block_41 */ | |
| } | |
| block block_41: | |
| /* preds: block_39 block_40 */ | |
| vec1 32 ssa_1317 = phi block_39: ssa_1321, block_40: ssa_3434 | |
| vec1 32 ssa_1259 = phi block_39: ssa_2426, block_40: ssa_3434 | |
| vec1 32 ssa_1251 = phi block_39: ssa_2422, block_40: ssa_3455 | |
| vec1 32 ssa_1244 = phi block_39: ssa_2418, block_40: ssa_3439 | |
| /* succs: block_43 */ | |
| } else { | |
| block block_42: | |
| /* preds: block_4 */ | |
| /* succs: block_43 */ | |
| } | |
| block block_43: | |
| /* preds: block_41 block_42 */ | |
| vec1 32 ssa_1316 = phi block_41: ssa_1317, block_42: ssa_3346 | |
| vec1 1 ssa_1267 = phi block_41: ssa_3344, block_42: ssa_3198 | |
| vec1 32 ssa_1258 = phi block_41: ssa_1259, block_42: ssa_3434 | |
| vec1 32 ssa_1250 = phi block_41: ssa_1251, block_42: ssa_3455 | |
| vec1 32 ssa_1243 = phi block_41: ssa_1244, block_42: ssa_3439 | |
| /* succs: block_45 */ | |
| } else { | |
| block block_44: | |
| /* preds: block_3 */ | |
| /* succs: block_45 */ | |
| } | |
| block block_45: | |
| /* preds: block_43 block_44 */ | |
| vec1 32 ssa_1315 = phi block_43: ssa_1316, block_44: ssa_3346 | |
| vec1 1 ssa_1266 = phi block_43: ssa_1267, block_44: ssa_3198 | |
| vec1 32 ssa_1257 = phi block_43: ssa_1258, block_44: ssa_3434 | |
| vec1 32 ssa_1249 = phi block_43: ssa_1250, block_44: ssa_3455 | |
| vec1 32 ssa_1242 = phi block_43: ssa_1243, block_44: ssa_3439 | |
| /* succs: block_47 */ | |
| } else { | |
| block block_46: | |
| /* preds: block_2 */ | |
| /* succs: block_47 */ | |
| } | |
| block block_47: | |
| /* preds: block_45 block_46 */ | |
| vec1 32 ssa_1314 = phi block_45: ssa_1315, block_46: ssa_3346 | |
| vec1 1 ssa_1265 = phi block_45: ssa_1266, block_46: ssa_3198 | |
| vec1 32 ssa_1256 = phi block_45: ssa_1257, block_46: ssa_3434 | |
| vec1 32 ssa_1248 = phi block_45: ssa_1249, block_46: ssa_3455 | |
| vec1 32 ssa_1241 = phi block_45: ssa_1242, block_46: ssa_3439 | |
| /* succs: block_49 */ | |
| } else { | |
| block block_48: | |
| /* preds: block_1 */ | |
| /* succs: block_49 */ | |
| } | |
| block block_49: | |
| /* preds: block_47 block_48 */ | |
| vec1 32 ssa_1313 = phi block_47: ssa_1314, block_48: ssa_3346 | |
| vec1 1 ssa_1264 = phi block_47: ssa_1265, block_48: ssa_3198 | |
| vec1 32 ssa_1255 = phi block_47: ssa_1256, block_48: ssa_3434 | |
| vec1 32 ssa_1247 = phi block_47: ssa_1248, block_48: ssa_3455 | |
| vec1 32 ssa_1240 = phi block_47: ssa_1241, block_48: ssa_3439 | |
| /* succs: block_51 */ | |
| } else { | |
| block block_50: | |
| /* preds: block_0 */ | |
| /* succs: block_51 */ | |
| } | |
| block block_51: | |
| /* preds: block_49 block_50 */ | |
| vec1 32 ssa_1312 = phi block_49: ssa_1313, block_50: ssa_3346 | |
| vec1 1 ssa_1263 = phi block_49: ssa_1264, block_50: ssa_3198 | |
| vec1 32 ssa_1254 = phi block_49: ssa_1255, block_50: ssa_3434 | |
| vec1 32 ssa_1246 = phi block_49: ssa_1247, block_50: ssa_3455 | |
| vec1 32 ssa_1239 = phi block_49: ssa_1240, block_50: ssa_3439 | |
| vec1 32 ssa_1186 = fmul ssa_1239, ssa_1246 | |
| vec1 32 ssa_1187 = fadd ssa_1186, ssa_1254 | |
| vec1 32 ssa_2463 = bcsel ssa_1263, ssa_1187, ssa_1312 | |
| vec1 32 ssa_2225 = load_const (0xfffffffc /* -nan */) | |
| vec1 32 ssa_2226 = iand ssa_1688.x, ssa_2225 | |
| intrinsic store_ssbo (ssa_2463, ssa_3440, ssa_2226) (0, 0, 4, 0) /* wrmask= */ /* access=0 */ /* align_mul=4 */ /* align_offset=0 */ | |
| /* succs: block_52 */ | |
| block block_52: | |
| } |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment