gistfile1.vhdl

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-----
----- util.vhd
-----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;

package util is
	function repl_unsigned(VAL: STD_LOGIC; SIZE: integer) return unsigned;
end util;

package body util is

	function repl_unsigned(VAL: STD_LOGIC; SIZE: integer) return unsigned is
		variable RESULT : unsigned(SIZE - 1 downto 0);
	begin
		for i in 0 to SIZE - 1 loop
			RESULT(i) := VAL;
		end loop;
		return RESULT;
	end;

end util;

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-----
----- mintest.vhd
-----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--- Synthesis fails with this line uncommented
--library util;
--- ISIM fails here if the above line is NOT uncommented
use util.ALL;

entity mintest is
    Port ( v : out  unsigned (1 downto 0));
end mintest;

architecture Behavioral of mintest is

begin

--- ISIM fails to find the repl_unsigned function here
	v <= repl_unsigned('1', 2);

end Behavioral;