nandland go board 640x480 vga generator

nandland_vga.v

`default_nettype none
`timescale 1ns / 1ps


// 640x480 vga generator
// clk = 25Mhz
module vga_t(input i_clk,
             output reg o_hsync,
             output reg o_vsync,
             output reg [9:0] o_x,
             output reg [9:0] o_y,
             output reg o_blank);

//  Clock Summary 
//    Clock: go_vga|i_Clk | Frequency: 204.60 MHz | Target: 148.15 MHz
// 
//  Device Utilization Summary
//    LogicCells                  : 76/1280
//    PLBs                        : 17/160

  reg x_blank, y_blank;

  always @(posedge i_clk) begin
    if (o_x == 10'd799) begin
      o_x <= 10'd0;
      o_y <= (o_y == 10'd524) ? 10'd0 : (o_y + 10'd1);
    end else begin
      o_x <= o_x + 10'd1;
    end
  end

  always @(posedge i_clk) begin
    x_blank <= (o_x == 10'd639) ? 1 :
               (o_x == 10'd799) ? 0 : x_blank;
  end

  always @(posedge i_clk) begin
    y_blank <= (o_y == 10'd479) ? 1 :
               (o_y == 10'd524) ? 0 : y_blank;
  end

  always @(*) begin
    o_blank = x_blank | y_blank;
  end

  always @(posedge i_clk) begin
    o_hsync <= (o_x == (10'd640 + 10'd18)) ? 0 :
               (o_x == (10'd800 - 10'd50)) ? 1 : o_hsync;
  end

  always @(posedge i_clk) begin
    o_vsync <= (o_y == (10'd480 + 10'd10)) ? 0 :
               (o_y == (10'd525 - 10'd33)) ? 1 : o_vsync;
  end
endmodule

module go_vga(input        i_Clk,
              output       o_VGA_HSync,
              output       o_VGA_VSync,
              output [2:0] o_VGA_R,
              output [2:0] o_VGA_G,
              output [2:0] o_VGA_B);

  wire [9:0] vga_x;
  wire [9:0] vga_y;
  wire vga_blank;

  vga_t vga(i_Clk, o_VGA_HSync, o_VGA_VSync, vga_x, vga_y, vga_blank);
  assign o_VGA_R = vga_blank ? 3'd0 : vga_x[8:6];
  assign o_VGA_G = vga_blank ? 3'd0 : vga_y[8:6];
  assign o_VGA_B = vga_blank ? 3'd0 : vga_y[8:6];

endmodule