YAC512 real time decoder

YAC512_decode.v

//
//
//
module UDA1334(
		input iCLK,
		input [15:0] iLeft,
		input [15:0] iRight,
		output oSEL,
		output oCLK,
		output oDAT);

	// clock divide input 50Mhz to 1612903Hz
	reg [4:0] clk_div;
	initial clk_div = 5'b0;
	always @(posedge iCLK) begin
		clk_div <= (clk_div == 30) ? 5'b00000 : (clk_div + 1); 
	end

	// generate bitclock
	wire bit_clk;
	assign bit_clk = clk_div[4];
	assign oCLK = ~bit_clk;
	
	reg [6:0] bit_count;
	initial bit_count = 7'b0;
	
	always @(posedge bit_clk) begin
		// wrap after 34 bits
		bit_count <= (bit_count == 33) ? 7'b0000000 : (bit_count + 1);
	end
	
	// generate word selectclock
	wire word_sel;
	// high for 17bits and low for next 17bits
	assign word_sel = (bit_count < 17);
	assign oSEL = word_sel;
	
	// latch in new data on the negedge
	reg [33:0] data;
	always @(negedge word_sel) begin
		data <= { iLeft,  1'b0,
					 iRight, 1'b0 };
	end
	
	wire data_bit;
	assign data_bit = data[33-bit_count];
	assign oDAT = data_bit;
	
endmodule

//
//
//
module yac512stream(
	input iSY,
	input iDOAB,
	input iSMPAC,
	input iSMPBD,
	output [15:0] oLeft,
	output [15:0] oRight);
	
	reg [15:0] shift;
	
	reg [15:0] left;
	reg [15:0] right;
	
	initial shift <= 16'b0;
	initial left  <= 16'b0;
	initial right <= 16'b0;

	always @(negedge iSY) begin
		shift <= { iDOAB, shift[15:1] };
	end

	always @(negedge iSMPAC) begin
		left <= shift;
	end
	
	always @(negedge iSMPAC) begin
		right <= shift;
	end

	assign oLeft = left;
	assign oRight = right;

endmodule

//
//
//
module yac512(
		input CLOCK_50,
		output [2:0] GPIO_0,
		input  [3:0] GPIO_1);

	wire [15:0] left;
	wire [15:0] right;

	// input stream
	yac512stream stream(
		GPIO_1[0],
		GPIO_1[1],
		GPIO_1[2],
		GPIO_1[3],
		left,
		right);
		
	// wire up the output DAC
	UDA1334 dac(
		CLOCK_50,
		left,
		right,
		GPIO_0[1],
		GPIO_0[0],
		GPIO_0[2]);
	
endmodule