Verilog - simple PS/2 keyboad decoder

keyboard_decode.v

// PS/2 keyboard decoder for Altera DE1 Kit


// decode 7 seg
module decode_seven_seg(
	input  [3:0] dec,
	output [6:0] out);

	reg [6:0] val;
	initial val = 0;
	always @(*) begin
		case (dec)
		4'h0: val <= 7'b1000000;
		4'h1: val <= 7'b1111001;
		4'h2: val <= 7'b0100100;
		4'h3: val <= 7'b0110000;
		4'h4: val <= 7'b0011001;
		4'h5: val <= 7'b0010010;
		4'h6: val <= 7'b0000010;
		4'h7: val <= 7'b1111000;
		4'h8: val <= 7'b0000000;
		4'h9: val <= 7'b0011000;
		4'ha: val <= 7'b0001000;
		4'hb: val <= 7'b0000011;
		4'hc: val <= 7'b1000110;
		4'hd: val <= 7'b0100001;
		4'he: val <= 7'b0000110;
		4'hf: val <= 7'b0001110;
		endcase
	end	
	assign out = val;
endmodule


// keyboard decoder
module keyboard(
	input PS2_CLK,
	input PS2_DAT,
	output [6:0] HEX0,
	output [6:0] HEX1,
	output [9:0] LEDR);

	reg [9:0] temp;
	reg [7:0] data;
	reg [3:0] count;

	initial temp = 10'b0;
	initial data = 8'b11111111;
	initial count = 4'b0;
	
	always @(negedge PS2_CLK) begin
		// if all data has been clocked in
		if (count == 10) begin
			count <= 4'b0000;
			// extract data and latch it
			data  <= temp[8:1];
		// increment
		end else begin
			// clock data in
			temp  <= { PS2_DAT, temp[9:1] };
			count <= count + 4'b0001;
		end
	end

	// display latched data
	decode_seven_seg h0(.dec(data[3:0]), .out(HEX0));
	decode_seven_seg h1(.dec(data[7:4]), .out(HEX1));
	
	// show PS/2 lines activity on LEDs
	assign LEDR[0] = ~PS2_CLK;
	assign LEDR[1] = ~PS2_DAT;
	
endmodule