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Created January 12, 2020 19:25
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nandland go board seven segment display module
`default_nettype none
`timescale 1ns / 1ps
module seven_seg(input [3:0] val, output reg [6:0] seg);
// seg
//
// +--0--+
// 5 1
// +--6--+
// 4 2
// +--3--+
always @(*) begin
case (val)
// 6543210
4'h0: seg = 7'b1000000;
4'h1: seg = 7'b1111001;
4'h2: seg = 7'b0100100;
4'h3: seg = 7'b0110000;
4'h4: seg = 7'b0011001;
4'h5: seg = 7'b0010010;
4'h6: seg = 7'b0000010;
4'h7: seg = 7'b1111000;
4'h8: seg = 7'b0000000;
4'h9: seg = 7'b0011000;
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
endcase
end
endmodule
module go_seg(input [3:0] i_Switch, output [6:0] o_Seg1, output [6:0] o_Seg2);
reg [7:0] count = 0;
always @(posedge i_Switch[0]) begin
count <= count + 1;
end
seven_seg segl(count[3:0], o_Seg2);
seven_seg segh(count[7:4], o_Seg1);
endmodule
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