A simple verilog debouncer circuit

verilog_debounce.v

module debounce(
    input  clk,
    input  iKey,
    output oOut,
);
    reg [3:0] state;
    assign oOut = state[3];
    always @(posedge clk) begin
        if (iKey) begin
            state <= (state == 4'hf) ? 4'hf : (state + 1);
        end else begin
            state <= (state == 4'h0) ? 4'h0 : (state - 1);
        end
    end
endmodule