verilog power on reset

power_on_reset.v

`timescale 1 ns / 1 ps

module power_on_reset(input in_clk, output out_rst);

  reg [5:0] reset_cnt = 0;
  wire resetn = &reset_cnt;

  assign out_rst = !resetn;

  always @(posedge in_clk) begin
    reset_cnt <= reset_cnt + !resetn;
  end

endmodule

module test_bench();
  
  reg clk;
  
  wire rst;
  power_on_reset por(clk, rst);
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    clk <= 0;
    #1000 $finish;
  end
  
  always @(*) begin
    #1 clk <= ~clk;
  end
  
  reg [7:0] counter;
  
  always @(posedge clk) begin
    if (rst) begin
      counter <= 0;
    end else begin
      counter <= counter + 8'd1;
    end
  end
  
endmodule