ICEStick ICE40 PhaseLockedLoop example

PLL_Blink.v

`default_nettype none
`timescale 1ns / 1ps

module top(input CLK, output D5);

    wire pll_clk_out;
    wire BYPASS;
    wire RESETB;
    wire LOCKED;
    wire global_clk;
    wire rst = ~LOCKED;

    assign BYPASS = 0;
    assign RESETB = 1;

    // PLLOUT = (CLK_IN * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))

    // create a 48Mhz clock
    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .PLLOUT_SELECT("GENCLK"),
        .DIVR(4'b0000),
        .DIVF(7'b0011111),
        .DIVQ(3'b011),
        .FILTER_RANGE(3'b001)
    ) uut (
        .REFERENCECLK   (CLK),
        .PLLOUTGLOBAL   (pll_clk_out), // output frequency
        .BYPASS         (BYPASS),
        .RESETB         (RESETB),  // active low
        .LOCK           (LOCKED)   // active high
    );

    // create a global clock buffer
    SB_GB gclkbuf(.USER_SIGNAL_TO_GLOBAL_BUFFER(pll_clk_out),
                  .GLOBAL_BUFFER_OUTPUT(global_clk));

    // simple counter
    reg [25:0] count = 0;
    always @(posedge(global_clk)) begin
      count <= (count >= 48000000) ? 0 : count + 1;
    end

    // blink LED with 50% duty cycle
    assign D5 = (count > 24000000) ? 1 : 0;

endmodule