FPGA-384 notes

FPGA-384.md

FPGA-384

• Website: https://www.siliconfrog.co.uk/
• Schematics: https://www.siliconfrog.co.uk/PDF/FPGA384/FPGA384_Schematic.pdf
• Github: https://github.com/siliconfrog/fpga-384

Specifications

16Mhz clock on IOL_5A

Pinheaders

left       spec            pin      spi        inner  outer   spi     pin

o IOT_49 |                        |          | 3v3 o  o     |       | X
o IOT_50 |                 IOT_47 |          |     o  o     |       | X
o IOT_53 | R               IOT_45 |          |     o  o Gnd |       |
o IOT_52 | G               IOR_39 |          |     o  o     |       | IOT_49
o IOL_2B | B                      |          | Gnd o  o     |       | IOT_50
o IOL_2A |                 IOR_38 |          |     o  o     |       | IOR_36
o IOL_4A |                 IOR_35 |          |     o  o Gnd |       |
o IOL_4B |                        | CRESET_B |     o  o     |       | IOR_34
o IOL_5B |                        |          | 3v3 o  o     | CDONE |
o IOL_5A | CLK             IOB_24 |      SDO |     o  o Gnd |       |
o        | CDONE           IOB_25 |      SDI |     o  o     |       | IOL_5A
o IOB_27 | SS              IOB_26 |      SCK |     o  o     | SS    | IOB_27
o        | X                      |          | Gnd o  o     | CE1   | 

EEPROM connections

host    eeprom    ice40

MOSI <-> MOSI <-> SDO
MISO <-> MISO <-> SDI
SDK  <-> SCK  <-> SCK
CE1  <-> CS

25LC_EEPROM CS is active low, so set CE1 to High to disable the EEPROM CRESET_B is active low and will reset the FPGA

Programming

CRESET_B = 0
SS = 0
SCK = 1
delay(200ns)
CRESET_B = 1
delay(1200us)
SS = 1
for (int i=0; i<8; ++i)
    send_clock
send config image on MOSI most significant bit first on the falling edge of SCK
SCK should be between 1Mhz and 25Mhz
for (int i=0; i<100; ++i)
    send_clock
check CDONE == 1
send 49 additional dummy bits and 49 spi clock cycles