Simple sram verilog model

sram.v

`default_nettype none
`timescale 1ns / 1ps

//
// simple sram model (IS61WV25616EDBLL)
//
module sram(input [3:0] addr,   // address bus
            input ce,           // chip enable    (act. low)
            input we,           // write enable   (act. low)
            input oe,           // output enable  (act. low)
            input lb,           // low byte       (act. low)
            input ub,           // upper byte     (act. low)
            inout [15:0] data); // i/o data

  wire [15:0] d0 = { memu[0], meml[0] };    // debug
  wire [15:0] d1 = { memu[1], meml[1] };    // debug

  reg [7:0] meml[15:0];
  reg [7:0] memu[15:0];

  reg [7:0] outl;
  reg [7:0] outh;

  // read
  assign data = { (ce|oe|!we|ub) ? 8'bzzzzzzzz : memu[addr],
                  (ce|oe|!we|lb) ? 8'bzzzzzzzz : meml[addr] };

  // write
  always @* begin
    if (!ce & !we & oe) begin
      memu[addr] = ub ? memu[addr] : data[15:8];
      meml[addr] = lb ? meml[addr] : data[ 7:0];
    end
  end
endmodule

module top();

  reg ce;
  reg we;
  reg [3:0] addr;
  reg oe;
  reg lb;
  reg ub;
  wire [15:0] data;

  sram sram_t(addr, ce, we, oe, lb, ub, data);

  reg [15:0] din;
  assign data = we ? 16'dz : din;

  reg clk;

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;

    clk <= 0;

    #2 ce <= 1; we <= 1; addr <= 4'h0; oe <= 1; lb <= 1; ub <= 1; din <= 8'h00;  // non selected
    #2 we <= 1;
    #2 ce <= 0; we <= 0; addr <= 4'h0; oe <= 1; lb <= 0; ub <= 0; din <= 8'h12;  // write 0
    #2 we <= 1;
    #2 ce <= 0; we <= 0; addr <= 4'h1; oe <= 1; lb <= 0; ub <= 0; din <= 8'h34;  // write 1
    #2 we <= 1;
    #2 ce <= 0; we <= 1; addr <= 4'h0; oe <= 0; lb <= 0; ub <= 0; din <= 8'h00;  // read 0
    #2 we <= 1;
    #2 ce <= 0; we <= 1; addr <= 4'h1; oe <= 0; lb <= 0; ub <= 0; din <= 8'h00;  // read 1
    #2 we <= 1;
    #2 ce <= 1; we <= 1; addr <= 4'h0; oe <= 1; lb <= 1; ub <= 1; din <= 8'h00;  // ?
    #2 we <= 1;
    #2 ce <= 1; we <= 1; addr <= 4'h0; oe <= 1; lb <= 1; ub <= 1; din <= 8'h00;  // non selected

    #2 $finish;
  end

  always @* begin
    #1 clk <= !clk;
  end

endmodule

SRAM model is based on the IS61WV25616EDBLL part used in the Altera-DE1 FPGA dev board. This SRAM model is to be used to assist simulation. Note however that the SRAM size for this model is amazingly small.