*untested* state variable filter for icesid

svf.v

module mult(input                CLK,
            input         [15:0] iSig,
            input  signed [15:0] iCoef,
            output signed [15:0] oOut);

  wire signed [31:0] product;             // 16x16 product
  assign oOut = product[31:16];

  SB_MAC16 mac(
    .A(iSignal),
    .B(iCoef),
    .O(product),
    .CLK(CLK),
  );

  defparam mac.A_SIGNED = 1'b1;           // input is signed
  defparam mac.B_SIGNED = 1'b0;           // coefficient is unsigned
  defparam mac.TOPOUTPUT_SELECT = 2'b11;  // Mult16x16 data output
  defparam mac.BOTOUTPUT_SELECT = 2'b11;  // Mult16x16 data output
endmodule

module filter(
    input clk,
    input clkEn,
    input signed [15:0] iIn,
    
    input [10:0] iCutoff,
    input [3:0] iRes,
    
    output signed [15:0] oLP,
    output signed [15:0] oBP,
    output signed [15:0] oHP
    );

  reg signed [15:0] low;
  reg signed [15:0] high;
  reg signed [15:0] band;
  
  assign oLP = low;
  assign oBP = band;
  assign oHP = high;
  
  wire [15:0] cutCoef = iCutoff << 2;
  wire [15:0] resCoef = (~iRes) << 12;

  // 16x16 multiplier
  reg         [15:0] mulA;
  reg  signed [15:0] mulB;
  wire signed [15:0] mulOut;
  mult mul(clk, mulA, mulB, mulOut);

  initial begin
    state <= 0;
    low   <= 0;
    high  <= 0;
    band  <= 0;
    mulA  <= 0;
    mulB  <= 0;
  end
  
  reg [1:0] state;
  always @(posedge clk) begin
    if (clkEn) begin
      mulA  <= iCutoff;
      mulB  <= band;
      state <= 0;
    end else begin
      case (state)
      0: begin
        low   <= low + mulOut;          // low + (cutoff * band)
        mulA  <= iRes;
        mulB  <= band;
        state <= 1;
      end
      1: begin
        high  <= iIn - low - mulOut;    // in - low - (res * band)
        mulA  <= iCutoff;
        mulB  <= high;
        state <= 2;
      end
      2: begin
        band  <= band + mulOut;         // band + (cutoff * High)
        state <= 3;
      end
      endcase
    end
  end
endmodule