Data tiling example

README.md

Compile for LLVM-CPU, AArch64, with +i8mm extension, causing MaterializeEncoding to pick (8, 8, 8) tile sizes:

tools/iree-compile --iree-hal-target-backends=llvm-cpu --iree-llvm-target-triple=aarch64-none-linux-android29 --iree-llvm-target-cpu-features=+i8mm  --iree-flow-enable-data-tiling ~/matmul.mlir --mlir-disable-threading -o /tmp/a.vmfb --mlir-print-ir-after-all 2>/tmp/log

Compiler for VMVX with microkernels, causing dynamic tile sizes:

tools/iree-compile --iree-hal-target-backends=vmvx --iree-flow-enable-data-tiling --iree-vmvx-enable-microkernels ~/matmul.mlir --mlir-disable-threading -o /tmp/a.vmfb --mlir-print-ir-after-all 2>/tmp/log

matmul.mlir

func.func @matmul_DYNxDYNxi8_times_DYNxDYNxi8_into_DYNxDYNxi32(%lhs: tensor<?x?xi8>, %rhs: tensor<?x?xi8>, %acc: tensor<?x?xi32>) -> tensor<?x?xi32> {
  %result = linalg.matmul ins(%lhs, %rhs: tensor<?x?xi8>, tensor<?x?xi8>) outs(%acc: tensor<?x?xi32>) -> tensor<?x?xi32>
  return %result: tensor<?x?xi32>
}