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bkrepo/mesongxbb.dtsi

Created March 28, 2016 09:24
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mesongxbb.dtsi for Xen
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mesongxbb.dtsi
#include <dt-bindings/clock/gxbb.h>
#include <dt-bindings/gpio/gxbb.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/aml_gxbb.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
cpus:cpus {
#address-cells = <2>;
#size-cells = <0>;
#cooling-cells = <2>; /* min followed by max */
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
//timer=<&timer_f>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
//timer=<&timer_g>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
//timer=<&timer_h>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
//timer=<&timer_i>;
};
};
/*
timer{
compatible = "arm, meson-timer";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg= <0x0 0xc1109990 0x0 0x4 0x0 0xc1109988 0x0 0x4>;
timer_f:timer-f{
timer_name="MESON TIMER-F";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x03>;
interrupts = <0 60 1>;
bit_enable=<16>;
bit_mode=<12>;
bit_resolution=<0>;
reg= <0x0 0xc1109994 0x0 0x4>;
};
timer_g:timer-g{
timer_name="MESON TIMER-G";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x03>;
interrupts = <0 61 1>;
bit_enable=<17>;
bit_mode=<13>;
bit_resolution=<2>;
reg=<0x0 0xc1109998 0x0 0x4>;
};
timer_h:timer-h{
timer_name="MESON TIMER-H";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x03>;
interrupts = <0 62 1>;
bit_enable=<18>;
bit_mode=<14>;
bit_resolution=<4>;
reg=<0x0 0xc110999c 0x0 0x4>;
};
timer_i:timer-i{
timer_name="MESON TIMER-I";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x03>;
interrupts = <0 63 1>;
bit_enable=<19>;
bit_mode=<15>;
bit_resolution=<6>;
reg=<0x0 0xc11099a0 0x0 0x4>;
};
};
*/
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 0xff08>,
<GIC_PPI 14 0xff08>,
<GIC_PPI 11 0xff08>,
<GIC_PPI 10 0xff08>;
};
arm_pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 137 4>,
<0 138 4>,
<0 153 4>,
<0 154 4>;
};
meson_suspend:pm{
compatible = "amlogic, pm";
gxbaby-suspend;
reg = <0x0 0xc81000a8 0x0 0x4
0x0 0xc810023c 0x0 0x4>;
};
gpu:mali@d00c0000{
#cooling-cells = <2>; /* min followed by max */
compatible = "arm,mali-450";
interrupt-parent = <&gic>;
reg = <0 0xd00c0000 0 0x40000>, /*mali APB bus base address*/
<0 0xc883c000 0 0x00004>, /*hiubus base address for gpu clk cntl*/
<0 0xc8100000 0 0x00004>; /*aobus base address for gpu pmu domain*/
interrupts = <0 160 4>, <0 161 4>, <0 162 4>, <0 163 4>,
<0 164 4>, <0 165 4>, <0 166 4>, <0 167 4>,
<0 168 4>, <0 169 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU",
"IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1",
"IRQPP2", "IRQPPMMU2";
pmu_domain_config = <0x1 0x2 0x4 0x4 0x0 0x0 0x0 0x0 0x0 0x1 0x2 0x0>;
pmu_switch_delay = <0xffff> ;
num_of_pp = <3> ;
def_clock = <3> ;
sc_mpp = <3>;/* number of pp used most of time.*/
tbl = <&clk125_cfg &clk285_cfg &clk400_cfg &clk500_cfg &clk666_cfg &clk800_cfg>;
clocks = <&clock CLK_FPLL_DIV3>,
<&clock CLK_FPLL_DIV4>,
<&clock CLK_FPLL_DIV5>,
<&clock CLK_FPLL_DIV7>,
<&clock GP0_PLL>,
<&clock CLK_MALI>,
<&clock CLK_MALI_0>,
<&clock CLK_MALI_1>;
clock-names =
"fclk_div3",
"fclk_div4",
"fclk_div5",
"fclk_div7",
"gp0_pll",
"clk_mali",
"clk_mali_0",
"clk_mali_1";
/*control_interval x keep_count == 900 - 1000ms */
control_interval = <200>;
dvfs_tbl = <&gpu_dvfs_tbl>;
clk125_cfg:clk125_cfg {
clk_freq = <125000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <30 120>;
};
clk250_cfg:clk250_cfg {
clk_freq = <250000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <80 170>;
};
clk285_cfg:clk285_cfg {
clk_freq = <285000000>;
clk_parent = "fclk_div7";
clkp_freq = <285000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <100 190>;
};
clk400_cfg:clk400_cfg {
clk_freq = <400000000>;
clk_parent = "fclk_div5";
clkp_freq = <400000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <152 207>;
};
clk500_cfg:clk500_cfg {
clk_freq = <500000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <180 220>;
};
clk666_cfg:clk666_cfg {
clk_freq = <666000000>;
clk_parent = "fclk_div3";
clkp_freq = <666000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <210 236>;
};
clk800_cfg:clk800_cfg {
clk_freq = <792000000>;
clk_parent = "gp0_pll";
clkp_freq = <792000000>;
voltage = <1150>;
keep_count = <5>;
threshold = <230 255>;
};
};
gic: interrupt-controller@c4301000{
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xc4301000 0 0x1000>,
<0x0 0xc4302000 0 0x2000>,
<0x0 0xc4304000 0 0x2000>,
<0x0 0xc4306000 0 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
aml_restart{
compatible = "aml, restart";
sys_reset = <0x84000009>;
sys_poweroff = <0x84000008>;
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0xC4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xC4000003>;
migrate = <0xC4000005>;
};
secmon {
compatible = "aml,secmon";
memory-region = <&secmon_reserved>;
in_base_func = <0x82000020>;
out_base_func = <0x82000021>;
};
securitykey {
compatible = "aml, securitykey";
storage_query = <0x82000060>;
storage_read = <0x82000061>;
storage_write = <0x82000062>;
storage_tell = <0x82000063>;
storage_verify = <0x82000064>;
storage_status = <0x82000065>;
storage_list = <0x82000067>;
storage_remove = <0x82000068>;
storage_in_func = <0x82000023>;
storage_out_func = <0x82000024>;
storage_block_func = <0x82000025>;
storage_size_func = <0x82000027>;
};
cpu_iomap{
compatible = "amlogic,iomap";
#address-cells=<2>;
#size-cells=<2>;
ranges;
io_cbus_base{
reg = <0x0 0xc1100000 0x0 0x100000>;
};
io_apb_base{
reg = <0x0 0xd0000000 0x0 0x200000>;
};
io_aobus_base{
reg = <0x0 0xc8100000 0x0 0x100000>;
};
};
cpufreq-meson {
compatible = "amlogic, cpufreq-scpi";
status = "okay";
clocks = <&scpi_dvfs 0>;
clock-names = "cpu_clk";
};
amlogic-watchdog{
compatible = "amlogic, gx-wdt";
status = "disable";
default_timeout=<10>;
reset_watchdog_method=<1>;//0:sysfs,1:kernel
reset_watchdog_time=<2>;
shutdown_timeout=<10>;
firmware_timeout=<6>;
suspend_timeout=<6>;
reg = <0x0 0xc11098d0 0x0 0x10>;
clocks = <&clock CLK_XTAL>;
};
clock: meson_clock {
compatible = "amlogic, gxbb-clock";
reg = <0x0 0xc883c000 0x0 0x1000>, /* HIU BUS*/
<0x0 0xc8100000 0x0 0x1000>; //AOBUS
#clock-cells = <1>;
#reset-cells = <1>;
sys_max = <1536000000>;
};
pinmux: pinmux{
compatible = "amlogic, pinmux-gxbb";
dev_name = "pinmux";
#pinmux-cells=<2>;
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xc1109880 0x0 0x10>;
ranges;
gpio: banks@c11080b0 {
reg = <0x0 0xc88344b0 0x0 0x28>,
<0x0 0xc88344e8 0x0 0x14>,
<0x0 0xc8834120 0x0 0x14>,
<0x0 0xc8834430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpio_ao: ao-bank@c1108030 {
reg = <0x0 0xc8100014 0x0 0x8>,
<0x0 0xc810002c 0x0 0x4>,
<0x0 0xc8100024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
eth_pins:eth_pins{
amlogic,setmask =<6 0x3fff>;
amlogic,clrmask =<6 0xc000>,
<5 0x3c0000f0>,
<4 0x300>;
amlogic,pins="GPIOZ_0","GPIOZ_1","GPIOZ_2","GPIOZ_3",
"GPIOZ_4","GPIOZ_5","GPIOZ_6","GPIOZ_7",
"GPIOZ_8","GPIOZ_9","GPIOZ_10","GPIOZ_11",
"GPIOZ_12","GPIOZ_13","GPIOZ_15";
};
remote_pins:remote_pin{
amlogic,setmask = <AO 0x1>;
amlogic,pins = "GPIOAO_7";
};
ao_uart_pins:ao_uart{
amlogic,setmask=<AO 0x1800>;
amlogic,pins="GPIOAO_0", "GPIOAO_1";
};
ao_b_uart_pins:ao_b_uart{
amlogic,setmask=<AO 0x1800000>;
amlogic,pins="GPIOAO_4", "GPIOAO_5";
};
a_uart_pins:a_uart{
amlogic,setmask=<4 0x3c00>;
amlogic,pins="GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15";
};
b_uart_pins:b_uart{
amlogic,setmask=<2 0x30000000>;
amlogic,pins="GPIODV_24", "GPIODV_25";
};
c_uart_pins:c_uart{
amlogic,setmask=<1 0xc0000>;
amlogic,pins="GPIOY_13", "GPIOY_14";
};
wifi_32k_pins:wifi_32k_pins{
amlogic,setmask=<2 0x40000000>;
amlogic,clrmask=<2 0x400000
3 0x8000>;
amlogic,pins="GPIOX_19";
};
sd_clk_cmd_pins:sd_clk_cmd_pins{
amlogic,setmask=<2 0x00000c00>,
<AO 0x00001800>;
amlogic,pins = "CARD_2","CARD_3"; /* CARD_2:CLK, CARD_3:CMD */
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sd_all_pins:sd_all_pins{
amlogic,setmask=<2 0x0000fc00>,
<AO 0x00001800>;
amlogic,pins="CARD_0","CARD_1","CARD_2","CARD_3","CARD_4","CARD_5";
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sd_1bit_pins:sd_1bit_pins{
amlogic,setmask=<2 0x00008c00>,
<AO 0x00001800>;
amlogic,pins = "CARD_1","CARD_2","CARD_3";
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins{
amlogic,setmask=<2 0x00000c00>,
<8 0x00000600>;
amlogic,pins = "CARD_2","CARD_3"; /* CARD_2:CLK, CARD_3:CMD */
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sd_1bit_uart_pins:sd_1bit_uart_pins{
amlogic,setmask=<2 0x00008c00>,
<8 0x00000600>;
amlogic,pins = "CARD_1","CARD_2","CARD_3";
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sd_to_ao_uart_pins:sd_to_ao_uart_pins{
amlogic,setmask=<AO 0x00001800>;
amlogic,clrmask=<8 0x00000600>;
amlogic,pins = "GPIOAO_0","GPIOAO_1";
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
ao_to_sd_uart_pins:ao_to_sd_uart_pins{
amlogic,setmask=<8 0x00000600>;
amlogic,clrmask=<AO 0x00001800>,
<2 0x00003000>;
amlogic,pins = "CARD_4","CARD_5";
amlogic,enable-output=<1>; /* 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
emmc_clk_cmd_pins:emmc_clk_cmd_pins{
amlogic,setmask=<4 0xc00c0000>;
amlogic,pins = "BOOT_8","BOOT_10"; /** BOOT_10:CMD, BOOT_8:CLK */
amlogic,enable-output=<1>; /** 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
emmc_all_pins:emmc_all_pins{
amlogic,setmask=<4 0xc00c0000>; /*sdhc c*/
amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
"BOOT_5","BOOT_6","BOOT_7","BOOT_8","BOOT_10";
amlogic,enable-output=<1>; /** 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sdio_clk_cmd_pins:sdio_clk_cmd_pins{
amlogic,setmask=<8 0x00000003>;
amlogic,pins = "GPIOX_4","GPIOX_5"; /** GPIOX_5:CMD, GPIOX_4:CLK */
amlogic,enable-output=<1>; /** 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
sdio_all_pins:sdio_all_pins{
amlogic,setmask=<8 0x0000003f>;
amlogic,pins = "GPIOX_0","GPIOX_1","GPIOX_2","GPIOX_3","GPIOX_4","GPIOX_5";
amlogic,enable-output=<1>; /** 0:output, 1:input */
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
/*cam_gpio_b: cam_gpio_b{
amlogic,setmask=<5 0xf0>;
amlogic,clrmask=<4 0x300
5 0xc000000
6 0x1ff3>;
amlogic,pins = "GPIOZ_0","GPIOZ_1","GPIOZ_3","GPIOZ_4","GPIOZ_5","GPIOZ_6","GPIOZ_7","GPIOZ_8","GPIOZ_9","GPIOZ_10","GPIOZ_11";
};
cam_gpio_a: cam_gpio_a{
amlogic,setmask=<2 0x3f0000>;
amlogic,clrmask=<1 0x7030ff
3 0x37>;
amlogic,pins = "GPIOY_1","GPIOY_0","GPIOY_2","GPIOY_15","GPIOY_16",
"GPIOY_3","GPIOY_4","GPIOY_5","GPIOY_6",
"GPIOY_7","GPIOY_8","GPIOY_9","GPIOY_10";
};*/
conf_nand_pulldown: conf_nand_pulldown{
amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
"BOOT_5","BOOT_6","BOOT_7","BOOT_15";
amlogic,pullup=<0>;
amlogic,pullupen=<1>;
};
conf_nand_pullup: conf_nand_pullup{
amlogic,pins = "BOOT_8", "BOOT_10";
amlogic,pullup=<1>;
amlogic,pullupen=<1>;
};
all_nand_pins: all_nand_pins{
amlogic,setmask=<4 0x7ff00000>;
amlogic,clrmask=<0 0x80000
4 0x800c0000
5 0xf>;
amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
"BOOT_5","BOOT_6","BOOT_7","BOOT_8","BOOT_9",
"BOOT_10","BOOT_11","BOOT_12","BOOT_13",
"BOOT_14","BOOT_15","BOOT_16","BOOT_17";
amlogic,enable-output=<1>;
};
nand_cs_pins: nand_cs{
amlogic,setmask=<4 0xc000000>;
amlogic,clrmask=<4 0x40000>;
amlogic,pins = "BOOT_8","BOOT_9";
};
hdmitx_hpd: hdmitx_hpd {
amlogic,setmask=<1 0x04000000>;
amlogic,pins="GPIOH_0";
};
hdmitx_ddc: hdmitx_ddc {
amlogic,setmask=<1 0x03000000>;
amlogic,pins="GPIOH_1", "GPIOH_2";
};
hdmitx_aocec: hdmitx_aocec {
amlogic,setmask=<AO 0x00008000>;
amlogic,clrmask=<AO 0x00024000
AO2 0x00000001>;
amlogic,pins="GPIOAO_12";
};
hdmitx_eecec: hdmitx_eecec {
amlogic,setmask=<AO 0x00004000>;
amlogic,clrmask=<AO 0x00028000
AO2 0x00000001>;
amlogic,pins="GPIOAO_12";
};
/*p200 i2c-A multiplex with usb PWR*/
a_i2c_master:a_i2c{
amlogic,setmask=<7 0xc000000>;
amlogic,clrmask=<0 0x18c0 2 0x30000000 5 0x1800>;
amlogic,pins="GPIODV_24","GPIODV_25";
};
b_i2c_master:b_i2c{
amlogic,setmask=<7 0x3000000>;
amlogic,clrmask=<0 0x600 2 0xc000000 5 0x700>;
amlogic,pins="GPIODV_26","GPIODV_27";
};
c_i2c_master:c_i2c{
amlogic,setmask=<7 0xc00000>;
amlogic,clrmask=<3 0x700000>;
amlogic,pins="GPIODV_28","GPIODV_29";
};
d_i2c_master:d_i2c{
amlogic,setmask=<4 0xc>;
amlogic,clrmask=<2 0x3000000 3 0x1000>;
amlogic,pins="GPIOX_16","GPIOX_17";
};
dvb_p_ts0_pins: dvb_p_ts0_pins {
amlogic,setmask = <3 0x37>;
amlogic,clrmask = <2 0xf0000 1 0x30ff>;
amlogic,pins = "GPIOY_0","GPIOY_1","GPIOY_2", "GPIOY_3","GPIOY_4","GPIOY_5","GPIOY_6","GPIOY_7","GPIOY_8","GPIOY_9","GPIOY_10";
};
dvb_s_ts0_pins: dvb_s_ts0_pins {
amlogic,setmask = <3 0x17>;
amlogic,clrmask = <2 0xf0000 1 0x7>;
amlogic,pins = "GPIOY_0","GPIOY_1","GPIOY_2","GPIOY_3";
};
};
cpu_version{
reg=<0x0 0xc8100220 0x0 0x4>;
};
meson_clk_msr{
compatible = "amlogic, gxbb_measure";
reg = <0x0 0xc110875c 0x0 0x4
0x0 0xc1108764 0x0 0x4>;
};
i2c_a: i2c@c1108500{ /*I2C-A*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-A";
status = "disabled";
reg = <0x0 0xc1108500 0x0 0x20>;
device_id = <1>;
pinctrl-names="default";
pinctrl-0=<&a_i2c_master>;/*p200 i2c-A multiplex with usb PWR*/
#address-cells = <1>;
#size-cells = <0>;
use_pio = <0>;
master_i2c_speed = <300000>;
clocks = <&clock CLK_81>;
clock-names = "clk_i2c";
resets = <&clock GCLK_IDX_I2C>;
};
i2c_b: i2c@c11087c0{ /*I2C-B*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-B";
status = "disabled";
reg = <0x0 0xc11087c0 0x0 0x20>;
device_id = <2>;
pinctrl-names="default";
pinctrl-0=<&b_i2c_master>;
#address-cells = <1>;
#size-cells = <0>;
use_pio = <0>;
master_i2c_speed = <300000>;
clocks = <&clock CLK_81>;
clock-names = "clk_i2c";
resets = <&clock GCLK_IDX_I2C>;
};
i2c_c: i2c@c11087e0{ /*I2C-C*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-C";
status = "disabled";
reg = <0x0 0xc11087e0 0x0 0x20>;
device_id = <3>;
pinctrl-names="default";
pinctrl-0=<&c_i2c_master>;
#address-cells = <1>;
#size-cells = <0>;
use_pio = <0>;
master_i2c_speed = <300000>;
clocks = <&clock CLK_81>;
clock-names = "clk_i2c";
resets = <&clock GCLK_IDX_I2C>;
};
i2c_d: i2c@c1108d20{ /*I2C-D*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-D";
status = "disabled";
reg = <0x0 0xc1108d20 0x0 0x20>;
device_id = <4>;
pinctrl-names="default";
pinctrl-0=<&d_i2c_master>;
#address-cells = <1>;
#size-cells = <0>;
use_pio = <0>;
master_i2c_speed = <300000>;
clocks = <&clock CLK_81>;
clock-names = "clk_i2c";
resets = <&clock GCLK_IDX_I2C>;
};
efuse: efuse{
compatible = "amlogic, efuse";
read_cmd = <0x82000030>;
write_cmd = <0x82000031>;
get_max_cmd = <0x82000033>;
key = <&efusekey>;
resets = <&clock GCLK_IDX_EFUSE>;
reset-names = "efuse_clk";
status = "disabled";
};
efusekey:efusekey{
keynum = <4>;
key0 = <&key0>;
key1 = <&key1>;
key2 = <&key2>;
key3 = <&key3>;
key0:key0{
keyname = "mac";
offset = <0>;
size = <6>;
};
key1:key1{
keyname = "mac_bt";
offset = <6>;
size = <6>;
};
key2:key2{
keyname = "mac_wifi";
offset = <12>;
size = <6>;
};
key3:key3{
keyname = "usid";
offset = <18>;
size = <16>;
};
};
mailbox: mhu@c883c400 {
compatible = "amlogic, meson_mhu";
reg = <0x0 0xc883c400 0x0 0x4c>, /* MHU registers */
<0x0 0xc8013000 0x0 0x800>; /* Payload area */
interrupts = <0 209 8>, /* low priority interrupt */
<0 210 8>; /* high priority interrupt */
#mbox-cells = <1>;
mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
mboxes = <&mailbox 0 &mailbox 1>;
};
scpi_clocks {
compatible = "arm,scpi-clks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-clk-indexed";
#clock-cells = <1>;
clock-indices = <0>;
clock-output-names = "vcpu";
};
};
meson-remote {
compatible = "amlogic, aml_remote";
dev_name = "meson-remote";
status = "ok";
remote_ao_offset = <0x580>; /* 0x400 + (0x20 + idx)<<2 -- old ; 0x400 + (0x60 +idx)<<2 --new */
interrupts = <0 196 1>;
pinctrl-names = "default";
pinctrl-0 = <&remote_pins>;
};
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0xc8834000 0x0 0x4>;
};
audio_data:audio_data {
compatible = "amlogic, audio_data";
query_licence_cmd = <0x82000050>;
status = "disabled";
};
saradc: saradc {
compatible = "amlogic, saradc";
status = "okay";
interrupts = <0 9 1>;
interrupt-names = "saradc_int";
clocks = <&clock CLK_XTAL>;
clock-names = "saradc_clk";
resets = <&clock GCLK_IDX_SARADC>;
reg = <0x0 0xc1108680 0x0 0x30
0x0 0xc883c3d8 0x0 0x08>;
};
};/* end of / */
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