memory-bram-regression-build-diff.txt

/* Automatically generated by Amaranth 0.4.dev183+gfc85feb.d2 | /* Automatically generated by Amaranth 0.4.dev184+g8c4a15a.d2
/* Generated by Yosys 0.40 (git sha1 a1bb0255d, ccache clang    /* Generated by Yosys 0.40 (git sha1 a1bb0255d, ccache clang 

module top(clk100_0__io, rst_0__io, led_0__io);                 module top(clk100_0__io, rst_0__io, led_0__io);
  reg \$auto$verilog_backend.cc:2352:dump_module$2  = 0;          reg \$auto$verilog_backend.cc:2352:dump_module$2  = 0;
                                                              >   wire [32:0] \$1 ;
  wire [32:0] \$2 ;                                               wire [32:0] \$2 ;
  wire [32:0] \$3 ;                                           <
  (* keep = "TRUE" *)                                             (* keep = "TRUE" *)
  wire cd_sync_clk100_0__i;                                       wire cd_sync_clk100_0__i;
  wire cd_sync_rst_0__i;                                          wire cd_sync_rst_0__i;
  wire clk;                                                       wire clk;
  input clk100_0__io;                                             input clk100_0__io;
  wire clk100_0__io;                                              wire clk100_0__io;
  reg [31:0] counter = 32'd0;                                     reg [31:0] counter = 32'd0;
  reg [31:0] \counter$next ;                                      reg [31:0] \counter$next ;
  output led_0__io;                                               output led_0__io;
  wire led_0__io;                                                 wire led_0__io;
  wire [12:0] mem_r_addr;                                         wire [12:0] mem_r_addr;
  wire [31:0] mem_r_data;                                         wire [31:0] mem_r_data;
                                                              >   wire mem_r_en;
  wire [12:0] mem_w_addr;                                         wire [12:0] mem_w_addr;
  wire [31:0] mem_w_data;                                         wire [31:0] mem_w_data;
  wire mem_w_en;                                                  wire mem_w_en;
  wire pin_led_0_led_0__o;                                        wire pin_led_0_led_0__o;
  wire rst;                                                       wire rst;
  input rst_0__io;                                                input rst_0__io;
  wire rst_0__io;                                                 wire rst_0__io;
  reg [31:0] mem [7999:0];                                    |   reg [31:0] \$read  [7999:0];
  initial begin                                               <
    mem[0] = 32'd0;                                           <
    mem[1] = 32'd0;                                           <
    mem[2] = 32'd0;                                           <
###
# omitting lines
###
   mem[7999] = 32'd0;                                        <
  end                                                         <
  always @(posedge clk) begin                                     always @(posedge clk) begin
    mem[mem_w_addr] <= mem_w_data;                            |     \$read [mem_w_addr] <= mem_w_data;
  end                                                             end
  reg [12:0] _0_;                                             |   reg [31:0] _0_;
  always @(posedge clk) begin                                     always @(posedge clk) begin
    _0_ <= mem_r_addr;                                        |     _0_ <= \$read [mem_r_addr];
  end                                                         |     if (1'h1 && mem_r_addr == mem_w_addr)
  assign mem_r_data = mem[_0_];                               |       _0_ <= mem_w_data;
  assign \$3  = counter + 1'h1;                               |   end
                                                              >   initial _0_ = 32'd0;
                                                              >   assign mem_r_data = _0_;
                                                              >   assign \$2  = counter + 1'h1;
  always @(posedge clk)                                           always @(posedge clk)
    counter <= \counter$next ;                                      counter <= \counter$next ;
  cd_sync cd_sync (                                               cd_sync cd_sync (
    .clk(clk),                                                      .clk(clk),
    .clk100_0__i(cd_sync_clk100_0__i),                              .clk100_0__i(cd_sync_clk100_0__i),
    .rst(rst),                                                      .rst(rst),
    .rst_0__i(cd_sync_rst_0__i)                                     .rst_0__i(cd_sync_rst_0__i)
  );                                                              );
  pin_clk100_0 pin_clk100_0 (                                     pin_clk100_0 pin_clk100_0 (
    .clk100_0__i(cd_sync_clk100_0__i),                              .clk100_0__i(cd_sync_clk100_0__i),
    .clk100_0__io(clk100_0__io)                                     .clk100_0__io(clk100_0__io)
  );                                                              );
  pin_led_0 pin_led_0 (                                           pin_led_0 pin_led_0 (
    .led_0__io(led_0__io),                                          .led_0__io(led_0__io),
    .led_0__o(pin_led_0_led_0__o)                                   .led_0__o(pin_led_0_led_0__o)
  );                                                              );
  pin_rst_0 pin_rst_0 (                                           pin_rst_0 pin_rst_0 (
    .rst_0__i(cd_sync_rst_0__i),                                    .rst_0__i(cd_sync_rst_0__i),
    .rst_0__io(rst_0__io)                                           .rst_0__io(rst_0__io)
  );                                                              );
                                                              >   write write (
                                                              >   );
  always @* begin                                                 always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$2 ) begin        if (\$auto$verilog_backend.cc:2352:dump_module$2 ) begin 
    \counter$next  = \$3 [31:0];                              |     \counter$next  = \$2 [31:0];
    if (rst) begin                                                  if (rst) begin
      \counter$next  = 32'd0;                                         \counter$next  = 32'd0;
    end                                                             end
  end                                                             end
  assign \$2  = \$3 ;                                         |   assign \$1  = \$2 ;
                                                              >   assign mem_r_en = 1'h1;
  assign pin_led_0_led_0__o = mem_r_data[0];                      assign pin_led_0_led_0__o = mem_r_data[0];
  assign mem_r_addr = counter[14:2];                              assign mem_r_addr = counter[14:2];
  assign mem_w_en = 1'h1;                                         assign mem_w_en = 1'h1;
  assign mem_w_data = counter;                                    assign mem_w_data = counter;
  assign mem_w_addr = counter[12:0];                              assign mem_w_addr = counter[12:0];
                                                              > endmodule
                                                              >
                                                              > module write();
                                                              >   wire \$empty_module_filler ;
endmodule                                                       endmodule

memory-bram-regression.py

from amaranth import Module, Signal, Elaboratable, Const
from amaranth.hdl.mem import Memory
from amaranth_boards.cmod_s7 import CmodS7_Platform
from amaranth.back import verilog

# This tests whether or not memory is instantiated as block RAM or
# distributed RAM.

# Test with these commits of amaranth-hdl:
# 8c4a15a -> infers distributed RAM
# fc85feb -> infers block RAM

class MemoryBramRegression(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        # led as output
        led = platform.request('led', 0)

        # counter to produce data
        counter = Signal(32)

        # memory to be instantiated as BRAM
        mem = Memory(width=32, depth=8000)
        w = m.submodules.write = mem.write_port()
        r = m.submodules.read = mem.read_port()

        # Increase counter on every clock cycle
        m.d.sync += counter.eq(counter + 1)

        # Connect mem to counter and led
        # Address increments on every clock cycle,
        # Write data is the full counter value
        # Enable is only active on every other clock cycle
        # Read address is running slower by a factor 4
        # Led should blink (but that is irrelevant for the test case)

        m.d.comb += [
            w.addr.eq(counter[0:13]),
            w.data.eq(counter),
            w.en.eq(Const(1)),
            r.addr.eq(counter[2:15]),
            led.o.eq(r.data[0])
        ]
        return m

if __name__ == "__main__":
    top = MemoryBramRegression()
    platform = CmodS7_Platform(toolchain="Vivado")
    platform.build(top)