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Bastian Löher bl0x

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bl0x / make_parts.bash
Created August 8, 2023 00:04
extract relevant part information from gowin ide device_info.csv
awk -F, '{print " [\""$2"\", \""$4"\"],"}' \
~/opt/gowin/IDE/share/device/device_info.csv \
| sort | cat <(echo "parts = [") - <(echo "]") > parts.py
@bl0x
bl0x / gowin_pn_parse.py
Created August 8, 2023 00:08
match all parts and families of Gowin FPGAs with regexes
import re
from parts import parts
some_parts = [
"GW1NR-UV9QN88C6/I5",
"GW1N-LV1QN48C6/I5",
"GW1NZ-LV1QN48C6/I5",
"GW1NSR-LV4CQN48PC7/I6",
"GW1NR-LV9QN88PC6/I5",
"GW1N-UV4LQ144C6/I5",
@bl0x
bl0x / memory-bram-regression-build-diff.txt
Last active April 24, 2024 21:20
/* Automatically generated by Amaranth 0.4.dev183+gfc85feb.d2 | /* Automatically generated by Amaranth 0.4.dev184+g8c4a15a.d2
/* Generated by Yosys 0.40 (git sha1 a1bb0255d, ccache clang /* Generated by Yosys 0.40 (git sha1 a1bb0255d, ccache clang
module top(clk100_0__io, rst_0__io, led_0__io); module top(clk100_0__io, rst_0__io, led_0__io);
reg \$auto$verilog_backend.cc:2352:dump_module$2 = 0; reg \$auto$verilog_backend.cc:2352:dump_module$2 = 0;
> wire [32:0] \$1 ;
wire [32:0] \$2 ; wire [32:0] \$2 ;
wire [32:0] \$3 ; <
(* keep = "TRUE" *) (* keep = "TRUE" *)
wire cd_sync_clk100_0__i; wire cd_sync_clk100_0__i;