Collected results during pcilmr utility testing on different systems
- Ryzen 7 3700X (Zen 2, Gen4)
- Ryzen 7 5800X (Zen 3, Gen 4)
- Ryzen 5600X (Zen 3, Gen 4)
- Vegman Gen2 - Xeon Gold 6342 (Ice Lake, Gen4)
- Сompal SR220-2 - Xeon Gold 5418N (Sapphire Rapids, Gen5)
cpuinfo
$ cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 23
model : 113
model name : AMD Ryzen 7 3700X 8-Core Processor
stepping : 0
microcode : 0x8701021
cpu MHz : 2162.099
cache size : 512 KB
physical id : 0
siblings : 16
core id : 0
cpu cores : 8
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 16
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip rdpid overflow_recov succor smca sev sev_es
bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass retbleed smt_rsb srso
bogomips : 7186.84
TLB size : 3072 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 43 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]
Tree and scan
$ sudo ./pcilmr --scan
Links with Lane Margining at the Receiver capabilities:
0:3.1 -> 5:0.0 - Ready
6:0.0 -> 7:0.0
0:7.1 -> 8:0.0
0:8.1 -> 9:0.0
$ lspci -tv
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex
...
+-02.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.1-[05-07]----00.0-[06-07]----00.0-[07]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 [Radeon RX 5600 OEM/5600 XT / 5700/5700 XT]
| \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 HDMI Audio
...
+-07.1-[08]----00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function
+-08.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
...
vvvs
$ sudo ./lspci -vvvs 05:00.0
05:00.0 Class 0604: Device 1002:1478 (rev c1)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 36
IOMMU group: 16
Region 0: Memory at fcc00000 (32-bit, non-prefetchable) [size=16K]
Bus: primary=05, secondary=06, subordinate=07, sec-latency=0
I/O behind bridge: f000-ffff [size=4K] [16-bit]
Memory behind bridge: fcb00000-fcbfffff [size=1M] [32-bit]
Prefetchable memory behind bridge: fc00000000-fe0fffffff [size=8448M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [48] Vendor Specific Information: Len=08 <?>
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Upstream Port, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS-
AtomicOpsCap: Routing+ 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [320 v1] Latency Tolerance Reporting
Max snoop latency: 0ns
Max no snoop latency: 0ns
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
$ sudo ./lspci -vvvs 00:03.1
00:03.1 Class 0604: Device 1022:1483
Subsystem: Device 1022:1453
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin ? routed to IRQ 29
IOMMU group: 5
Bus: primary=00, secondary=05, subordinate=07, sec-latency=0
I/O behind bridge: f000-ffff [size=4K] [16-bit]
Memory behind bridge: fcb00000-fccfffff [size=2M] [32-bit]
Prefetchable memory behind bridge: fc00000000-fe0fffffff [size=8448M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 75W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCap: CRSVisible+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee00000 Data: 0000
Capabilities: [c0] Subsystem: Device 1022:1453
Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP- SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn+ NFERptEn+ FERptEn+
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?>
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
Results
$ sudo ./pcilmr 05:00.0
Link 0:3.1 -> 5:0.0
Negotiated Link Width: 16
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 0
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 23
Number of Voltage Steps: 0
Max Timing Offset: 50
Max Voltage Offset: 0
Max Lanes: 15
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 0
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 17
Number of Voltage Steps: 0
Max Timing Offset: 50
Max Voltage Offset: 0
Max Lanes: 15
----
Results:
Link 0:3.1 -> 5:0.0:
Rx(A) Lane 0 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 1 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 2 - Okay L 28.3% UI - 17.66ps - 13st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 3 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 4 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 5 - Bad L 17.4% UI - 10.87ps - 8st LIM, R 17.4% UI - 10.87ps - 8st LIM
Rx(A) Lane 6 - Bad L 15.2% UI - 9.51ps - 7st LIM, R 15.2% UI - 9.51ps - 7st LIM
Rx(A) Lane 7 - Bad L 19.6% UI - 12.23ps - 9st LIM, R 19.6% UI - 12.23ps - 9st LIM
Rx(A) Lane 8 - Bad L 19.6% UI - 12.23ps - 9st LIM, R 19.6% UI - 12.23ps - 9st LIM
Rx(A) Lane 9 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 10 - Bad L 19.6% UI - 12.23ps - 9st LIM, R 19.6% UI - 12.23ps - 9st LIM
Rx(A) Lane 11 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 12 - Bad L 15.2% UI - 9.51ps - 7st LIM, R 15.2% UI - 9.51ps - 7st LIM
Rx(A) Lane 13 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 14 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 15 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(F) Lane 0 - Okay L 26.5% UI - 16.54ps - 9st LIM, R 23.5% UI - 14.71ps - 8st LIM
Rx(F) Lane 1 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 2 - Bad L 14.7% UI - 9.19ps - 5st LIM, R 14.7% UI - 9.19ps - 5st LIM
Rx(F) Lane 3 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 4 - Bad L 17.6% UI - 11.03ps - 6st LIM, R 17.6% UI - 11.03ps - 6st LIM
Rx(F) Lane 5 - Bad L 17.6% UI - 11.03ps - 6st LIM, R 17.6% UI - 11.03ps - 6st LIM
Rx(F) Lane 6 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 7 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 8 - Okay L 23.5% UI - 14.71ps - 8st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 9 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 10 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 11 - Bad L 17.6% UI - 11.03ps - 6st LIM, R 17.6% UI - 11.03ps - 6st LIM
Rx(F) Lane 12 - Bad L 17.6% UI - 11.03ps - 6st LIM, R 17.6% UI - 11.03ps - 6st LIM
Rx(F) Lane 13 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
Rx(F) Lane 14 - Okay L 20.6% UI - 12.87ps - 7st LIM, R 20.6% UI - 12.87ps - 7st LIM
cpuinfo
% cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 25
model : 33
model name : AMD Ryzen 7 5800X 8-Core Processor
stepping : 0
microcode : 0xa201016
cpu MHz : 550.000
cache size : 512 KB
physical id : 0
siblings : 16
core id : 0
cpu cores : 8
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 16
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass srso
bogomips : 7600.15
TLB size : 2560 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 48 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]
Tree and scan
% ./lspci -tv
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex
+-01.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-01.2-[01-0a]----00.0-[02-0a]--+-03.0-[03-06]----00.0-[04-06]--+-03.0-[05]--
| | \-07.0-[06]--
| +-06.0-[07]----00.0 Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller
| +-08.0-[08]--+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP
| | +-00.1 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
| | \-00.3 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
| +-09.0-[09]----00.0 Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]
| \-0a.0-[0a]----00.0 Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]
+-01.3-[0b]----00.0 Micron/Crucial Technology P5 Plus NVMe PCIe SSD
+-02.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.1-[0c-0e]----00.0-[0d-0e]----00.0-[0e]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Navi 31 [Radeon RX 7900 XT/7900 XTX]
| \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Device ab30
+-04.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-05.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-07.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-07.1-[0f]----00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function
+-08.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-08.1-[10]--+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP
| +-00.1 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Cryptographic Coprocessor PSPCPP
| \-00.3 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
+-14.0 Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller
+-14.3 Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge
+-18.0 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 0
+-18.1 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 1
+-18.2 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 2
+-18.3 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 3
+-18.4 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 4
+-18.5 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 5
+-18.6 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 6
\-18.7 Advanced Micro Devices, Inc. [AMD] Matisse/Vermeer Data Fabric: Device 18h; Function 7
% sudo ./pcilmr --scan
Links with Lane Margining at Receiver capabilities:
0:8.1 -> 10:0.0
d:0.0 -> e:0.0 - Ready
0:7.1 -> f:0.0
2:a.0 -> a:0.0
0:1.2 -> 1:0.0 - Ready
2:8.0 -> 8:0.0
0:1.3 -> b:0.0 - Ready
2:9.0 -> 9:0.0
0:3.1 -> c:0.0 - Ready
vvvs
% sudo ./lspci -vvvs 00:03.1
00:03.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge (prog-if 00 [Normal decode])
Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin ? routed to IRQ 28
Bus: primary=00, secondary=0c, subordinate=0e, sec-latency=0
I/O behind bridge: e000-efff [size=4K] [16-bit]
Memory behind bridge: fcc00000-fcefffff [size=3M] [32-bit]
Prefetchable memory behind bridge: 7000000000-780fffffff [size=33024M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 75W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCap: CRSVisible+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee08000 Data: 0021
Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP- SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn+ NFERptEn+ FERptEn+
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 2 3 5 6 7 8 9 10 13 15
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid+ TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?>
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady- MargSoftReady-
Kernel driver in use: pcieport
% sudo ./lspci -vvvs 0c:00.0
0c:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch (rev 10) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 42
Region 0: Memory at fce00000 (32-bit, non-prefetchable) [size=16K]
Bus: primary=0c, secondary=0d, subordinate=0e, sec-latency=0
I/O behind bridge: e000-efff [size=4K] [16-bit]
Memory behind bridge: fcc00000-fcdfffff [size=2M] [32-bit]
Prefetchable memory behind bridge: 7000000000-780fffffff [size=33024M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [48] Vendor Specific Information: Len=08 <?>
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Upstream Port, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS-
AtomicOpsCap: Routing+ 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 1 2 3 4 7 8 10 12 13 14
Capabilities: [320 v1] Latency Tolerance Reporting
Max snoop latency: 0ns
Max no snoop latency: 0ns
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
Results
% sudo ./pcilmr 0c:00.0
Link 0:3.1 -> c:0.0
Negotiated Link Width: 16
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 0
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 23
Number of Voltage Steps: 0
Max Timing Offset: 50
Max Voltage Offset: 0
Max Lanes: 15
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 1
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 0
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 17
Number of Voltage Steps: 0
Max Timing Offset: 49
Max Voltage Offset: 0
Max Lanes: 15
Rx(A) Lane 0 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 1 - Bad L 19.6% UI - 12.23ps - 9st LIM, R 19.6% UI - 12.23ps - 9st LIM
Rx(A) Lane 2 - Bad L 17.4% UI - 10.87ps - 8st LIM, R 17.4% UI - 10.87ps - 8st LIM
Rx(A) Lane 3 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 4 - Bad L 17.4% UI - 10.87ps - 8st LIM, R 19.6% UI - 12.23ps - 9st LIM
Rx(A) Lane 5 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 6 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 7 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 8 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 9 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 10 - Okay L 28.3% UI - 17.66ps - 13st LIM, R 28.3% UI - 17.66ps - 13st LIM
Rx(A) Lane 11 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 12 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 13 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 14 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 15 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(F) Lane 0 - Okay L 25.9% UI - 16.21ps - 9st LIM, R 25.9% UI - 16.21ps - 9st LIM
Rx(F) Lane 1 - Bad L 17.3% UI - 10.81ps - 6st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 2 - Bad L 17.3% UI - 10.81ps - 6st LIM, R 17.3% UI - 10.81ps - 6st LIM
Rx(F) Lane 3 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
Rx(F) Lane 4 - Okay L 20.2% UI - 12.61ps - 7st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 5 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
Rx(F) Lane 6 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
Rx(F) Lane 7 - Bad L 14.4% UI - 9.01ps - 5st LIM, R 14.4% UI - 9.01ps - 5st LIM
Rx(F) Lane 8 - Okay L 20.2% UI - 12.61ps - 7st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 9 - Okay L 20.2% UI - 12.61ps - 7st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 10 - Okay L 20.2% UI - 12.61ps - 7st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 11 - Okay L 20.2% UI - 12.61ps - 7st LIM, R 20.2% UI - 12.61ps - 7st LIM
Rx(F) Lane 12 - Bad L 17.3% UI - 10.81ps - 6st LIM, R 17.3% UI - 10.81ps - 6st LIM
Rx(F) Lane 13 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
Rx(F) Lane 14 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
Rx(F) Lane 15 - Okay L 23.1% UI - 14.41ps - 8st LIM, R 23.1% UI - 14.41ps - 8st LIM
vvvs
% sudo ./lspci -vvvs 0d:00.0
0d:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch (rev 10) (prog-if 00 [Normal decode])
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 43
Bus: primary=0d, secondary=0e, subordinate=0e, sec-latency=0
I/O behind bridge: e000-efff [size=4K] [16-bit]
Memory behind bridge: fcc00000-fcdfffff [size=2M] [32-bit]
Prefetchable memory behind bridge: 7000000000-780fffffff [size=33024M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Downstream Port (Slot-), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <1us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- ARIFwd-
AtomicOpsCap: Routing+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee0d000 Data: 0021
Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [450 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
% sudo ./lspci -vvvs 0e:00.0
0e:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 31 [Radeon RX 7900 XT/7900 XTX] (rev c8) (prog-if 00 [VGA controller])
Subsystem: Tul Corporation / PowerColor Navi 31 [Radeon RX 7900 XT/7900 XTX]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 98
Region 0: Memory at 7000000000 (64-bit, prefetchable) [size=32G]
Region 2: Memory at 7800000000 (64-bit, prefetchable) [size=256M]
Region 4: I/O ports at e000 [size=256]
Region 5: Memory at fcc00000 (32-bit, non-prefetchable) [size=1M]
Expansion ROM at fcd00000 [disabled] [size=128K]
Capabilities: [48] Vendor Specific Information: Len=08 <?>
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 256 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <1us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Form Factor Dev Specific, EmergencyPowerReductionInit-
FRS-
AtomicOpsCap: 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn+
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee08000 Data: 0024
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [200 v1] Physical Resizable BAR
BAR 0: current size: 32GB, supported: 256MB 512MB 1GB 2GB 4GB 8GB 16GB 32GB
BAR 2: current size: 256MB, supported: 2MB 4MB 8MB 16MB 32MB 64MB 128MB 256MB
Capabilities: [240 v1] Power Budgeting <?>
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [2d0 v1] Process Address Space ID (PASID)
PASIDCap: Exec+ Priv+, Max PASID Width: 10
PASIDCtl: Enable- Exec- Priv-
Capabilities: [320 v1] Latency Tolerance Reporting
Max snoop latency: 1048576ns
Max no snoop latency: 1048576ns
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [450 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: amdgpu
Kernel modules: amdgpu
Results
% sudo ./pcilmr 0e:00.0
Link d:0.0 -> e:0.0
Negotiated Link Width: 16
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 1
Sample Reporting Method: 1
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 6
Number of Voltage Steps: 32
Max Timing Offset: 20
Max Voltage Offset: 5
Max Lanes: 15
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 1
Sample Reporting Method: 1
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 6
Number of Voltage Steps: 32
Max Timing Offset: 20
Max Voltage Offset: 5
Max Lanes: 15
Link d:0.0 -> e:0.0:
Rx(A) Lane 0 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 1 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 2 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 3 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 4 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 5 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 6 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 7 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 8 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 9 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 10 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 11 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 12 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 13 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 14 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(A) Lane 15 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 0 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 1 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 2 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 3 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 4 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 5 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 6 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 7 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 8 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 9 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 10 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 11 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 12 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 13 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 14 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
Rx(F) Lane 15 - Weird L 20.0% UI - 12.50ps - 6st THR, R 20.0% UI - 12.50ps - 6st THR, U 50.0 mV - 32st THR, D 50.0 mV - 32st THR
vvvs
% sudo ./lspci -vvvs 00:01.3
00:01.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge (prog-if 00 [Normal decode])
Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin ? routed to IRQ 27
Bus: primary=00, secondary=0b, subordinate=0b, sec-latency=0
I/O behind bridge: 0000f000-00000fff [disabled] [32-bit]
Memory behind bridge: fcf00000-fcffffff [size=1M] [32-bit]
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 75W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCap: CRSVisible+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee06000 Data: 0021
Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP- SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn+ NFERptEn+ FERptEn+
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0 1 2 3
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid+ TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?>
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady- MargSoftReady-
Kernel driver in use: pcieport
% sudo ./lspci -vvvs 0b:00.0
0b:00.0 Non-Volatile memory controller: Micron/Crucial Technology P5 Plus NVMe PCIe SSD (prog-if 02 [NVM Express])
Subsystem: Micron/Crucial Technology P5 Plus NVMe PCIe SSD
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 44
NUMA node: 0
Region 0: Memory at fcf00000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI-X: Enable+ Count=32 Masked-
Vector table: BAR=0 offset=00003000
PBA: BAR=0 offset=00002000
Capabilities: [60] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range BCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp+ 10BitTagReq- OBFF Via message, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 17s to 64s, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [2a0 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2d0 v1] Latency Tolerance Reporting
Max snoop latency: 1048576ns
Max no snoop latency: 1048576ns
Capabilities: [320 v1] Data Link Feature <?>
Capabilities: [330 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [360 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [700 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+
PortCommonModeRestoreTime=32us PortTPowerOnTime=20us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
T_CommonMode=0us LTR1.2_Threshold=32768ns
L1SubCtl2: T_PwrOn=20us
Kernel driver in use: nvme
Results
% sudo ./pcilmr 0b:00.0
Link 0:1.3 -> b:0.0
Negotiated Link Width: 4
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Error during caps reading.
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 1
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 15
Number of Voltage Steps: 63
Max Timing Offset: 50
Max Voltage Offset: 20
Max Lanes: 3
Link 0:1.3 -> b:0.0:
Rx(A) - Couldn't run test (Error during caps reading)
Rx(F) Lane 0 - Perfect L 33.3% UI - 20.83ps - 10st LIM, R 33.3% UI - 20.83ps - 10st LIM, U 101.6 mV - 32st NAK, D 101.6 mV - 32st NAK
Rx(F) Lane 1 - Perfect L 36.7% UI - 22.92ps - 11st LIM, R 40.0% UI - 25.00ps - 12st LIM, U 101.6 mV - 32st NAK, D 101.6 mV - 32st NAK
Rx(F) Lane 2 - Perfect L 40.0% UI - 25.00ps - 12st LIM, R 36.7% UI - 22.92ps - 11st LIM, U 101.6 mV - 32st NAK, D 101.6 mV - 32st NAK
Rx(F) Lane 3 - Perfect L 33.3% UI - 20.83ps - 10st LIM, R 33.3% UI - 20.83ps - 10st LIM, U 101.6 mV - 32st NAK, D 101.6 mV - 32st NAK
vvvs
% sudo ./lspci -vvvs 00:01.2
00:01.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge (prog-if 00 [Normal decode])
Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin ? routed to IRQ 26
Bus: primary=00, secondary=01, subordinate=0a, sec-latency=0
I/O behind bridge: f000-ffff [size=4K] [16-bit]
Memory behind bridge: fc400000-fc8fffff [size=5M] [32-bit]
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x8, ASPM L1, Exit Latency L1 <32us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 75W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCap: CRSVisible+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee04000 Data: 0021
Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge
Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP- SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn+ NFERptEn+ FERptEn+
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid+ TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?>
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
% sudo ./lspci -vvvs 01:00.0
01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] Matisse Switch Upstream (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 24
Bus: primary=01, secondary=02, subordinate=0a, sec-latency=0
I/O behind bridge: f000-ffff [size=4K] [16-bit]
Memory behind bridge: fc400000-fc8fffff [size=5M] [32-bit]
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Upstream Port, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75W
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x8, ASPM L1, Exit Latency L1 <32us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4 (downgraded)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS-
AtomicOpsCap: Routing+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0 3
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
Results
% sudo ./pcilmr 01:00.0
Link 0:1.2 -> 1:0.0
Negotiated Link Width: 4
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Error during caps reading.
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Error during caps reading.
----
Results:
Link 0:1.2 -> 1:0.0:
Rx(A) - Couldn't run test (Error during caps reading)
Rx(F) - Couldn't run test (Error during caps reading)
cpuinfo
# cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 25
model : 33
model name : AMD Ryzen 5 5600X 6-Core Processor
stepping : 2
microcode : 0xa201204
cpu MHz : 3601.662
cache size : 512 KB
physical id : 0
siblings : 12
core id : 0
cpu cores : 6
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 16
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass
bogomips : 7386.43
TLB size : 2560 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 48 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]
Tree and scan
# ./pcilmr --scan
Links with Lane Margining at Receiver capabilities:
2:8.0 -> 4:0.0
2:9.0 -> 5:0.0
2:a.0 -> 6:0.0
0:3.1 -> 7:0.0 - Ready
0:8.1 -> a:0.0
0:1.2 -> 1:0.0 - Ready
0:3.2 -> 8:0.0 - Ready
0:7.1 -> 9:0.0
# lspci -vvvt
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex
+-00.2 Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU
+-01.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-01.2-[01-06]----00.0-[02-06]--+-05.0-[03]----00.0 Intel Corporation I211 Gigabit Network Connection
| +-08.0-[04]--+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP
| | +-00.1 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
| | \-00.3 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
| +-09.0-[05]----00.0 Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]
| \-0a.0-[06]----00.0 Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]
+-02.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-03.1-[07]----00.0 Broadcom / LSI Fusion-MPT 12GSAS/PCIe Secure SAS38xx
+-03.2-[08]----00.0 Broadcom / LSI Fusion-MPT 12GSAS/PCIe Secure SAS38xx
+-04.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-05.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-07.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-07.1-[09]----00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function
+-08.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge
+-08.1-[0a]--+-00.0 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP
| +-00.1 Advanced Micro Devices, Inc. [AMD] Starship/Matisse Cryptographic Coprocessor PSPCPP
| +-00.3 Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller
| \-00.4 Advanced Micro Devices, Inc. [AMD] Starship/Matisse HD Audio Controller
...
vvvs
# ./lspci -vvvs 0:3.1
00:03.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge (prog-if 00 [Normal decode])
Subsystem: ASUSTeK Computer Inc. Device 8808
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin ? routed to IRQ 28
IOMMU group: 4
Bus: primary=00, secondary=07, subordinate=07, sec-latency=0
I/O behind bridge: e000-efff [size=4K] [16-bit]
Memory behind bridge: fce00000-fcffffff [size=2M] [32-bit]
Prefetchable memory behind bridge: fc200000-fc3fffff [size=2M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 16GT/s, Width x8, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis+ BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x8
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 75W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCap: CRSVisible+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis+
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee00000 Data: 0000
Capabilities: [c0] Subsystem: ASUSTeK Computer Inc. Device 8808
Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP- SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn+ NFERptEn+ FERptEn+
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 2 4 5 6 7
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
Capabilities: [370 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
L1SubCtl2:
Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?>
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Kernel driver in use: pcieport
# ./lspci -vvvs 7:0.0
07:00.0 Serial Attached SCSI controller: Broadcom / LSI Fusion-MPT 12GSAS/PCIe Secure SAS38xx
Subsystem: Broadcom / LSI 9500-8e Tri-Mode HBA
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 67
IOMMU group: 20
Region 0: Memory at fc300000 (64-bit, prefetchable) [size=1M]
Region 2: Memory at fc200000 (64-bit, prefetchable) [size=1M]
Region 4: Memory at fce00000 (32-bit, non-prefetchable) [size=1M]
Region 5: I/O ports at e000 [size=256]
Expansion ROM at fcf00000 [disabled] [size=256K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [70] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s unlimited, L1 <64us
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x8, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis+ BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x8
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR-
10BitTagComp+ 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis+
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: Upstream Port
Capabilities: [b0] MSI-X: Enable+ Count=128 Masked-
Vector table: BAR=0 offset=00002000
PBA: BAR=0 offset=00003000
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [148 v1] Power Budgeting <?>
Capabilities: [158 v1] Alternative Routing-ID Interpretation (ARI)
ARICap: MFVC- ACS-, Next Function: 0
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [168 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [188 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [1b0 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [218 v1] Dynamic Power Allocation <?>
Capabilities: [248 v1] Vendor Specific Information: ID=0002 Rev=4 Len=100 <?>
Capabilities: [348 v1] Vendor Specific Information: ID=0001 Rev=1 Len=038 <?>
Capabilities: [380 v1] Data Link Feature <?>
Kernel driver in use: mpt3sas
Results
$ sudo ./pcilmr -T -V 7:00.0
Link 0:3.1 -> 7:0.0
Negotiated Link Width: 8
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 0
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 23
Number of Voltage Steps: 0
Max Timing Offset: 50
Max Voltage Offset: 0
Max Lanes: 15
Receiver = Rx(F)
Independent Error Sampler: 1
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 0
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 0
Number of Timing Steps: 7
Number of Voltage Steps: 32
Max Timing Offset: 20
Max Voltage Offset: 5
Max Lanes: 7
Results:
Link 0:3.1 -> 7:0.0:
Rx(A) Lane 0 - Bad L 17.4% UI - 10.87ps - 8st LIM, R 17.4% UI - 10.87ps - 8st LIM
Rx(A) Lane 1 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 2 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 3 - Okay L 26.1% UI - 16.30ps - 12st LIM, R 26.1% UI - 16.30ps - 12st LIM
Rx(A) Lane 4 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 5 - Okay L 23.9% UI - 14.95ps - 11st LIM, R 23.9% UI - 14.95ps - 11st LIM
Rx(A) Lane 6 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(A) Lane 7 - Okay L 21.7% UI - 13.59ps - 10st LIM, R 21.7% UI - 13.59ps - 10st LIM
Rx(F) Lane 0 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 1 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 2 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 3 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 4 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 5 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 6 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
Rx(F) Lane 7 - Weird T 20.0% UI - 12.50ps - 7st NAK, V 50.0 mV - 32st NAK
cpuinfo
cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 106
model name : Intel(R) Xeon(R) Gold 6342 CPU @ 2.80GHz
stepping : 6
microcode : 0xd0003a5
cpu MHz : 2800.000
cache size : 36864 KB
physical id : 0
siblings : 48
core id : 0
cpu cores : 24
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 27
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid fsrm md_clear pconfig flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs mmio_stale_data eibrs_pbrsb gds
bogomips : 5600.00
clflush size : 64
cache_alignment : 64
address sizes : 46 bits physical, 57 bits virtual
power management:
Tree
lspci -PP | grep "/"
0000:00:1c.0/01:00.0 Ethernet controller: Intel Corporation I211 Gigabit Network Connection (rev 03)
0000:00:1c.1/02:00.0 Ethernet controller: Intel Corporation I211 Gigabit Network Connection (rev 03)
0000:00:1c.2/03:00.0 Ethernet controller: Intel Corporation I211 Gigabit Network Connection (rev 03)
0000:00:1c.3/04:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 04)
0000:00:1c.3/04:00.0/05:00.0 VGA compatible controller: ASPEED Technology, Inc. ASPEED Graphics Family (rev 41)
0000:00:1c.4/06:00.0 Ethernet controller: Intel Corporation I211 Gigabit Network Connection (rev 03)
0000:00:1c.5/07:00.0 Ethernet controller: Intel Corporation I211 Gigabit Network Connection (rev 03)
0000:16:02.0/17:00.0 Ethernet controller: Mellanox Technologies MT2892 Family [ConnectX-6 Dx]
0000:16:02.0/17:00.1 Ethernet controller: Mellanox Technologies MT2892 Family [ConnectX-6 Dx]
0000:97:02.0/98:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM173X
0000:b0:02.0/b1:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM173X
0000:c9:02.0/ca:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM173X
0000:c9:04.0/cb:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM173X
Results
# ./pcilmr --margin 17:00.0
Link 16:2.0 -> 17:0.0
Negotiated Link Width: 8
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Running on Intel Ice Lake CPU.
Applying next quirks for margining process:
- Set MaxVoltageOffset to 12 (120 mV).
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 0
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 63
Number of Voltage Steps: 127
Max Timing Offset: 50
Max Voltage Offset: 12
Max Lanes: 0
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 1
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 15
Number of Voltage Steps: 32
Max Timing Offset: 50
Max Voltage Offset: 50
Max Lanes: 0
----
Results:
Link 16:2.0 -> 17:0.0:
Rx(A) Lane 0 - Perfect T 40.5% UI - 25.30ps LIM, U 50.1 mV LIM, D 50.1 mV LIM
Rx(A) Lane 1 - Bad T 40.5% UI - 25.30ps LIM, U 47.2 mV LIM, D 46.3 mV LIM
Rx(A) Lane 2 - Bad T 38.9% UI - 24.31ps LIM, U 44.4 mV LIM, D 45.4 mV LIM
Rx(A) Lane 3 - Bad T 36.5% UI - 22.82ps LIM, U 45.4 mV LIM, D 45.4 mV LIM
Rx(A) Lane 4 - Bad T 41.3% UI - 25.79ps LIM, U 45.4 mV LIM, D 46.3 mV LIM
Rx(A) Lane 5 - Bad T 38.1% UI - 23.81ps LIM, U 46.3 mV LIM, D 47.2 mV LIM
Rx(A) Lane 6 - Perfect T 40.5% UI - 25.30ps LIM, U 52.9 mV LIM, D 52.0 mV LIM
Rx(A) Lane 7 - Bad T 38.1% UI - 23.81ps LIM, U 47.2 mV LIM, D 48.2 mV LIM
Rx(F) Lane 0 - Okay L 20.0% UI - 12.50ps LIM, R 20.0% UI - 12.50ps LIM, U 203.1 mV LIM, D 203.1 mV LIM
Rx(F) Lane 1 - Okay L 20.0% UI - 12.50ps LIM, R 20.0% UI - 12.50ps LIM, U 171.9 mV LIM, D 187.5 mV LIM
Rx(F) Lane 2 - Okay L 20.0% UI - 12.50ps LIM, R 20.0% UI - 12.50ps LIM, U 187.5 mV LIM, D 187.5 mV LIM
Rx(F) Lane 3 - Okay L 20.0% UI - 12.50ps LIM, R 20.0% UI - 12.50ps LIM, U 203.1 mV LIM, D 203.1 mV LIM
Rx(F) Lane 4 - Okay L 26.7% UI - 16.67ps LIM, R 26.7% UI - 16.67ps LIM, U 234.4 mV LIM, D 234.4 mV LIM
Rx(F) Lane 5 - Okay L 23.3% UI - 14.58ps LIM, R 23.3% UI - 14.58ps LIM, U 218.8 mV LIM, D 203.1 mV LIM
Rx(F) Lane 6 - Okay L 23.3% UI - 14.58ps LIM, R 23.3% UI - 14.58ps LIM, U 218.8 mV LIM, D 203.1 mV LIM
Rx(F) Lane 7 - Okay L 23.3% UI - 14.58ps LIM, R 23.3% UI - 14.58ps LIM, U 234.4 mV LIM, D 234.4 mV LIM
cpuinfo
$ cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Gold 5418N
stepping : 8
microcode : 0x2b0004b1
cpu MHz : 1800.000
cache size : 46080 KB
physical id : 0
siblings : 48
core id : 0
cpu cores : 24
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 3600.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
Tree and scan
# ./pcilmr --scan
Links with Lane Margining at Receiver capabilities:
29:1.0 -> 2a:0.0 - Ready
aa:1.0 -> ab:0.0 - Ready
4f:5.0 -> 52:0.0 - Ready
4f:7.0 -> 53:0.0 - Ready
~$ lspci -tv
-+-[0000:ff]-+-00.0 Intel Corporation Device 324c
| +-00.1 Intel Corporation Device 324c
...
+-[0000:aa]-+-00.0 Intel Corporation Device 09a2
...
| \-01.0-[ab]----00.0 Mellanox Technologies MT2910 Family [ConnectX-7]
...
+-[0000:4f]-+-00.0 Intel Corporation Device 09a2
...
| +-01.0-[50]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller 172Xa/172Xb
| +-03.0-[51]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller 172Xa/172Xb
| +-05.0-[52]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM173X
| \-07.0-[53]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM173X
...
+-[0000:29]-+-00.0 Intel Corporation Device 09a2
...
| \-01.0-[2a]--+-00.0 Mellanox Technologies MT2894 Family [ConnectX-6 Lx]
| \-00.1 Mellanox Technologies MT2894 Family [ConnectX-6 Lx]
...
\-[0000:00]-+-00.0 Intel Corporation Device 09a2
...
+-0e.0-[01]----00.0 Renesas Technology Corp. uPD720202 USB 3.0 Host Controller
+-0f.0-[02-03]----00.0-[03]----00.0 ASPEED Technology, Inc. ASPEED Graphics Family
vvvs
# ./lspci -vvvs 29:1.0
29:01.0 PCI bridge: Intel Corporation Device 352a (rev 04) (prog-if 00 [Normal decode])
Subsystem: Intel Corporation Device 0000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 44
NUMA node: 0
Region 0: Memory at 202ffff00000 (64-bit, non-prefetchable) [size=128K]
Bus: primary=29, secondary=2a, subordinate=2a, sec-latency=0
I/O behind bridge: 6000-6fff [size=4K] [16-bit]
Memory behind bridge: a9d00000-a9efffff [size=2M] [32-bit]
Prefetchable memory behind bridge: 202ffa000000-202ffeffffff [size=80M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #9, Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <16us
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x8
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #1, PowerLimit 0W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+
Control: AttnInd Off, PwrInd Off, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState-
RootCap: CRSVisible+
RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP+ LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd+
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS+
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR+ 10BitTagReq+ OBFF Disabled, ARIFwd+
AtomicOpsCtl: ReqEn+ EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [94] Subsystem: Intel Corporation Device 0000
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable+ 64bit-
Address: fee00038 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap+
HeaderLog: 20000010 2a0100ff 00000001 380901c0
RootCmd: CERptEn- NFERptEn- FERptEn-
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [220 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [190 v1] Vendor Specific Information: ID=0003 Rev=0 Len=00a <?>
Capabilities: [1a0 v1] Downstream Port Containment
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr-
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f
Source: 0000
Capabilities: [150 v1] Precision Time Measurement
PTMCap: Requester:- Responder:+ Root:+
PTMClockGranularity: 2ns
PTMControl: Enabled:+ RootSelected:+
PTMEffectiveGranularity: 2ns
Capabilities: [280 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00
Status: NegoPending- InProgress-
Capabilities: [a30 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0 1 2 3 4 5 6 7
Capabilities: [a90 v1] Data Link Feature <?>
Capabilities: [a9c v1] Physical Layer 16.0 GT/s <?>
Capabilities: [ae0 v1] Extended Capability ID 0x2a
Capabilities: [edc v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [b20 v1] Extended Capability ID 0x2b
Kernel driver in use: pcieport
# ./lspci -vvvs 2a:0.0
2a:00.0 Ethernet controller: Mellanox Technologies MT2894 Family [ConnectX-6 Lx]
Subsystem: Mellanox Technologies MT2894 Family [ConnectX-6 Lx]
Physical Slot: 1
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
NUMA node: 0
Region 0: Memory at 202ffc000000 (64-bit, prefetchable) [size=32M]
Expansion ROM at a9e00000 [disabled] [size=1M]
Capabilities: [60] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x8, ASPM not supported
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x8
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR-
10BitTagComp+ 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn+
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [48] Vital Product Data
Product Name: ConnectX-6 Lx EN adapter card, 25GbE, Dual-port SFP28, PCIe 4.0 x8, No Crypto
Read-only fields:
[PN] Part number: MCX631102AN-ADAT
[EC] Engineering changes: A6
[V2] Vendor specific: MCX631102AN-ADAT
[SN] Serial number: MT2040X06499
[V3] Vendor specific: 0a8732526a06eb118000043f72d2cd12
[VA] Vendor specific: MLX:MN=MLNX:CSKU=V2:UUID=V3:PCI=V0:MODL=CX631102A
[V0] Vendor specific: PCIeGen4 x8
[RV] Reserved: checksum good, 1 byte(s) reserved
End
Capabilities: [9c] MSI-X: Enable+ Count=64 Masked-
Vector table: BAR=0 offset=00002000
PBA: BAR=0 offset=00003000
Capabilities: [c0] Vendor Specific Information: Len=18 <?>
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 08, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
ARICap: MFVC- ACS-, Next Function: 1
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [180 v1] Single Root I/O Virtualization (SR-IOV)
IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ 10BitTagReq-
IOVSta: Migration-
Initial VFs: 8, Total VFs: 8, Number of VFs: 0, Function Dependency Link: 00
VF offset: 2, stride: 1, Device ID: 101e
Supported Page Size: 000007ff, System Page Size: 00000001
Region 0: Memory at 0000202ffe800000 (64-bit, prefetchable)
VF Migration: offset: 00000000, BIR: 0
Capabilities: [1c0 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [230 v1] Access Control Services
ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [320 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [370 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [420 v1] Data Link Feature <?>
Kernel driver in use: mlx5_core
Results
$ sudo ./pcilmr -T -V 2a:00.0
Link 29:1.0 -> 2a:0.0
Negotiated Link Width: 8
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 0
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 63
Number of Voltage Steps: 127
Max Timing Offset: 50
Max Voltage Offset: 12
Max Lanes: 0
Error Count Limit = 4
Parallel Lanes: 1
Receiver = Rx(F)
Independent Error Sampler: 1
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 15
Number of Voltage Steps: 32
Max Timing Offset: 50
Max Voltage Offset: 50
Max Lanes: 0
Error Count Limit = 4
Parallel Lanes: 1
Results:
Link 29:1.0 -> 2a:0.0:
Rx(A) Lane 0 - Bad T 15.1% UI - 9.42ps - 19st LIM, U 81.3 mV - 86st LIM, D 82.2 mV - 87st LIM
Rx(A) Lane 1 - Bad T 15.1% UI - 9.42ps - 19st LIM, U 78.4 mV - 83st LIM, D 78.4 mV - 83st LIM
Rx(A) Lane 2 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 77.5 mV - 82st LIM, D 78.4 mV - 83st LIM
Rx(A) Lane 3 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 76.5 mV - 81st LIM, D 76.5 mV - 81st LIM
Rx(A) Lane 4 - Bad T 14.3% UI - 8.93ps - 18st LIM, U 85.0 mV - 90st LIM, D 84.1 mV - 89st LIM
Rx(A) Lane 5 - Bad T 14.3% UI - 8.93ps - 18st LIM, U 81.3 mV - 86st LIM, D 80.3 mV - 85st LIM
Rx(A) Lane 6 - Bad T 15.1% UI - 9.42ps - 19st LIM, U 85.0 mV - 90st LIM, D 86.9 mV - 92st LIM
Rx(A) Lane 7 - Bad T 15.1% UI - 9.42ps - 19st LIM, U 85.0 mV - 90st LIM, D 80.3 mV - 85st LIM
Rx(F) Lane 0 - Okay L 30.0% UI - 18.75ps - 9st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 203.1 mV - 13st LIM, D 203.1 mV - 13st LIM
Rx(F) Lane 1 - Okay L 26.7% UI - 16.67ps - 8st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 218.8 mV - 14st LIM, D 218.8 mV - 14st LIM
Rx(F) Lane 2 - Okay L 26.7% UI - 16.67ps - 8st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 234.4 mV - 15st LIM, D 234.4 mV - 15st LIM
Rx(F) Lane 3 - Perfect L 30.0% UI - 18.75ps - 9st LIM, R 30.0% UI - 18.75ps - 9st LIM, U 234.4 mV - 15st LIM, D 234.4 mV - 15st LIM
Rx(F) Lane 4 - Perfect L 30.0% UI - 18.75ps - 9st LIM, R 30.0% UI - 18.75ps - 9st LIM, U 203.1 mV - 13st LIM, D 203.1 mV - 13st LIM
Rx(F) Lane 5 - Okay L 26.7% UI - 16.67ps - 8st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 171.9 mV - 11st LIM, D 171.9 mV - 11st LIM
Rx(F) Lane 6 - Bad L 26.7% UI - 16.67ps - 8st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 265.6 mV - 17st LIM, D 265.6 mV - 17st LIM
Rx(F) Lane 7 - Okay L 26.7% UI - 16.67ps - 8st LIM, R 26.7% UI - 16.67ps - 8st LIM, U 250.0 mV - 16st LIM, D 250.0 mV - 16st LIM
vvvs
# ./lspci -vvvs aa:1.0
aa:01.0 PCI bridge: Intel Corporation Device 352a (rev 04) (prog-if 00 [Normal decode])
Subsystem: Intel Corporation Device 0000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 67
NUMA node: 1
Region 0: Memory at 209ffff00000 (64-bit, non-prefetchable) [size=128K]
Bus: primary=aa, secondary=ab, subordinate=ab, sec-latency=0
I/O behind bridge: c000-cfff [size=4K] [16-bit]
Memory behind bridge: e2200000-e22fffff [size=1M] [32-bit]
Prefetchable memory behind bridge: 209ffa000000-209ffdffffff [size=64M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #9, Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <16us
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 32GT/s, Width x16
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #2, PowerLimit 0W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+
Control: AttnInd Off, PwrInd Off, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState-
RootCap: CRSVisible+
RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP+ LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd+
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS+
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR+ 10BitTagReq+ OBFF Disabled, ARIFwd+
AtomicOpsCtl: ReqEn+ EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [94] Subsystem: Intel Corporation Device 0000
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable+ 64bit-
Address: fee00038 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap+
HeaderLog: 4a080001 ab000001 fd21003d 00000000
RootCmd: CERptEn- NFERptEn- FERptEn-
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [220 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [190 v1] Vendor Specific Information: ID=0003 Rev=0 Len=00a <?>
Capabilities: [1a0 v1] Downstream Port Containment
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr-
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f
Source: 0000
Capabilities: [150 v1] Precision Time Measurement
PTMCap: Requester:- Responder:+ Root:+
PTMClockGranularity: 2ns
PTMControl: Enabled:+ RootSelected:+
PTMEffectiveGranularity: 2ns
Capabilities: [280 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00
Status: NegoPending- InProgress-
Capabilities: [a30 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Capabilities: [a90 v1] Data Link Feature <?>
Capabilities: [a9c v1] Physical Layer 16.0 GT/s <?>
Capabilities: [ae0 v1] Extended Capability ID 0x2a
Capabilities: [edc v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [b20 v1] Extended Capability ID 0x2b
Kernel driver in use: pcieport
# ./lspci -vvvs ab:0.0
ab:00.0 Infiniband controller: Mellanox Technologies MT2910 Family [ConnectX-7]
Subsystem: Mellanox Technologies MT2910 Family [ConnectX-7]
Physical Slot: 2
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
NUMA node: 1
Region 0: Memory at 209ffa000000 (64-bit, prefetchable) [size=32M]
Expansion ROM at e2200000 [disabled] [size=1M]
Capabilities: [60] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM not supported
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 32GT/s, Width x16
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR-
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR- 10BitTagReq+ OBFF Disabled,
AtomicOpsCtl: ReqEn+
LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [48] Vital Product Data
Product Name: NVIDIA ConnectX-7 adapter card, 200Gb/s NDR200 IB, Single-port OSFP, PCIe 5.0 x16, Secure boot, No Crypto
Read-only fields:
[PN] Part number: MCX75310AAS-HEAT
[EC] Engineering changes: A5
[V2] Vendor specific: MCX75310AAS-HEAT
[SN] Serial number: MT2247XZ02YV
[V3] Vendor specific: 56dca528bb7ced118000b83fd2e824ee
[VA] Vendor specific: MLX:MN=MLNX:CSKU=V2:UUID=V3:PCI=V0:MODL=CX75310AA
[V0] Vendor specific: PCIeGen5 x16
[VU] Vendor specific: MT2247XZ02YVMLNXS0D0F0
[RV] Reserved: checksum good, 1 byte(s) reserved
End
Capabilities: [9c] MSI-X: Enable+ Count=64 Masked-
Vector table: BAR=0 offset=00002000
PBA: BAR=0 offset=00003000
Capabilities: [c0] Vendor Specific Information: Len=18 <?>
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 08, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
ARICap: MFVC- ACS-, Next Function: 0
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [180 v1] Single Root I/O Virtualization (SR-IOV)
IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ 10BitTagReq-
IOVSta: Migration-
Initial VFs: 16, Total VFs: 16, Number of VFs: 0, Function Dependency Link: 00
VF offset: 1, stride: 1, Device ID: 101e
Supported Page Size: 000007ff, System Page Size: 00000001
Region 0: Memory at 0000209ffc000000 (64-bit, prefetchable)
VF Migration: offset: 00000000, BIR: 0
Capabilities: [1c0 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 2 6 9 10 11 12 13 14 15
Capabilities: [320 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [370 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [3b0 v1] Extended Capability ID 0x2a
Capabilities: [420 v1] Data Link Feature <?>
Kernel driver in use: mlx5_core
Results
$ sudo ./pcilmr -T -V ab:00.0
Link aa:1.0 -> ab:0.0
Negotiated Link Width: 16
Link Speed: 32.0 GT/s = Gen 5
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 0
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 63
Number of Voltage Steps: 127
Max Timing Offset: 50
Max Voltage Offset: 12
Max Lanes: 0
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 1
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 15
Number of Voltage Steps: 32
Max Timing Offset: 0
Max Voltage Offset: 0
Max Lanes: 15
Warning: Vendor chose not to report the Max Timing Offset.
Utility will use its max possible value - 50 (50% UI).
Warning: Vendor chose not to report the Max Voltage Offset.
Utility will use its max possible value - 50 (500 mV).
Results:
Link aa:1.0 -> ab:0.0:
Rx(A) Lane 0 - Bad T 13.5% UI - 4.22ps - 17st LIM, U 55.7 mV - 59st LIM, D 55.7 mV - 59st LIM
Rx(A) Lane 1 - Bad T 14.3% UI - 4.46ps - 18st LIM, U 56.7 mV - 60st LIM, D 56.7 mV - 60st LIM
Rx(A) Lane 2 - Bad T 13.5% UI - 4.22ps - 17st LIM, U 59.5 mV - 63st LIM, D 58.6 mV - 62st LIM
Rx(A) Lane 3 - Bad T 15.1% UI - 4.71ps - 19st LIM, U 58.6 mV - 62st LIM, D 61.4 mV - 65st LIM
Rx(A) Lane 4 - Bad T 15.1% UI - 4.71ps - 19st LIM, U 59.5 mV - 63st LIM, D 60.5 mV - 64st LIM
Rx(A) Lane 5 - Bad T 14.3% UI - 4.46ps - 18st LIM, U 60.5 mV - 64st LIM, D 63.3 mV - 67st LIM
Rx(A) Lane 6 - Bad T 13.5% UI - 4.22ps - 17st LIM, U 63.3 mV - 67st LIM, D 62.4 mV - 66st LIM
Rx(A) Lane 7 - Bad T 15.1% UI - 4.71ps - 19st LIM, U 61.4 mV - 65st LIM, D 60.5 mV - 64st LIM
Rx(A) Lane 8 - Bad T 15.1% UI - 4.71ps - 19st LIM, U 60.5 mV - 64st LIM, D 60.5 mV - 64st LIM
Rx(A) Lane 9 - Bad T 13.5% UI - 4.22ps - 17st LIM, U 61.4 mV - 65st LIM, D 60.5 mV - 64st LIM
Rx(A) Lane 10 - Bad T 12.7% UI - 3.97ps - 16st LIM, U 52.9 mV - 56st LIM, D 52.9 mV - 56st LIM
Rx(A) Lane 11 - Bad T 12.7% UI - 3.97ps - 16st LIM, U 58.6 mV - 62st LIM, D 57.6 mV - 61st LIM
Rx(A) Lane 12 - Bad T 11.9% UI - 3.72ps - 15st LIM, U 53.9 mV - 57st LIM, D 57.6 mV - 61st LIM
Rx(A) Lane 13 - Bad T 11.9% UI - 3.72ps - 15st LIM, U 51.0 mV - 54st LIM, D 52.0 mV - 55st LIM
Rx(A) Lane 14 - Bad T 12.7% UI - 3.97ps - 16st LIM, U 59.5 mV - 63st LIM, D 55.7 mV - 59st LIM
Rx(A) Lane 15 - Bad T 12.7% UI - 3.97ps - 16st LIM, U 58.6 mV - 62st LIM, D 58.6 mV - 62st LIM
Rx(F) - Attention: Vendor chose not to report the Max Timing Offset.
Utility used its max possible value (50% UI) for calculations of % UI and ps.
Keep in mind that for timing results of this receiver only steps values are reliable.
Rx(F) - Attention: Vendor chose not to report the Max Voltage Offset.
Utility used its max possible value (500 mV) for calculations of mV.
Keep in mind that for voltage results of this receiver only steps values are reliable.
Rx(F) Lane 0 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 1 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 343.8 mV - 22st LIM
Rx(F) Lane 2 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 343.8 mV - 22st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 3 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 4 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 5 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 343.8 mV - 22st LIM
Rx(F) Lane 6 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 343.8 mV - 22st LIM
Rx(F) Lane 7 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 8 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 9 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 10 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 343.8 mV - 22st LIM, D 359.4 mV - 23st LIM
Rx(F) Lane 11 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 12 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 328.1 mV - 21st LIM
Rx(F) Lane 13 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 343.8 mV - 22st LIM
Rx(F) Lane 14 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 328.1 mV - 21st LIM, D 343.8 mV - 22st LIM
Rx(F) Lane 15 - Perfect L 50.0% UI - 15.62ps - 15st NAK, R 50.0% UI - 15.62ps - 15st NAK, U 312.5 mV - 20st LIM, D 312.5 mV - 20st LIM
vvvs
# ./lspci -vvvs 4f:5.0
4f:05.0 PCI bridge: Intel Corporation Device 352c (rev 04) (prog-if 00 [Normal decode])
Subsystem: Intel Corporation Device 0000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 53
NUMA node: 0
Region 0: Memory at 204ffff20000 (64-bit, non-prefetchable) [size=128K]
Bus: primary=4f, secondary=52, subordinate=52, sec-latency=0
I/O behind bridge: f000-0fff [disabled] [16-bit]
Memory behind bridge: bdb00000-bdcfffff [size=2M] [32-bit]
Prefetchable memory behind bridge: 204000400000-2040005fffff [size=2M] [32-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #29, Speed 32GT/s, Width x4, ASPM L1, Exit Latency L1 <16us
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis+ BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd+ PwrInd+ HotPlug+ Surprise+
Slot #66, PowerLimit 0W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+
Control: AttnInd Off, PwrInd Off, Power+ Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState-
RootCap: CRSVisible+
RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP+ LTR+
10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd+
AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS+
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR+ 10BitTagReq+ OBFF Disabled, ARIFwd+
AtomicOpsCtl: ReqEn+ EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis+
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [94] Subsystem: Intel Corporation Device 0000
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable+ 64bit-
Address: fee00078 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap+
HeaderLog: 4a080001 52000004 fc010000 00000000
RootCmd: CERptEn- NFERptEn- FERptEn-
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
Capabilities: [220 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [190 v1] Vendor Specific Information: ID=0003 Rev=0 Len=00a <?>
Capabilities: [1a0 v1] Downstream Port Containment
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr-
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f
Source: 0000
Capabilities: [150 v1] Precision Time Measurement
PTMCap: Requester:- Responder:+ Root:+
PTMClockGranularity: 2ns
PTMControl: Enabled:+ RootSelected:+
PTMEffectiveGranularity: 2ns
Capabilities: [280 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00
Status: NegoPending- InProgress-
Capabilities: [a30 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0 1 2 3
Capabilities: [a90 v1] Data Link Feature <?>
Capabilities: [a9c v1] Physical Layer 16.0 GT/s <?>
Capabilities: [ae0 v1] Extended Capability ID 0x2a
Capabilities: [edc v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady-
Capabilities: [b20 v1] Extended Capability ID 0x2b
Kernel driver in use: pcieport
# ./lspci -vvvs 52:0.0
52:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM173X (prog-if 02 [NVM Express])
Subsystem: Samsung Electronics Co Ltd NVMe SSD Controller PM173X
Physical Slot: 66
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
NUMA node: 0
Region 0: Memory at bdc10000 (64-bit, non-prefetchable) [size=32K]
Expansion ROM at bdb00000 [disabled] [size=64K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM not supported
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis+ BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x4
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR-
10BitTagComp+ 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis+
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: Upstream Port
Capabilities: [b0] MSI-X: Enable+ Count=64 Masked-
Vector table: BAR=0 offset=00004000
PBA: BAR=0 offset=00003000
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC+ UnsupReq+ ACSViol-
UESvrt: DLP+ SDES+ TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [148 v1] Device Serial Number 46-29-01-11-99-38-25-00
Capabilities: [168 v1] Alternative Routing-ID Interpretation (ARI)
ARICap: MFVC- ACS-, Next Function: 0
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [178 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [198 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [1c0 v1] Lane Margining at the Receiver
PortCap: Uses Driver-
PortSta: MargReady+ MargSoftReady+
Capabilities: [1e8 v1] Single Root I/O Virtualization (SR-IOV)
IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ 10BitTagReq-
IOVSta: Migration-
Initial VFs: 32, Total VFs: 32, Number of VFs: 0, Function Dependency Link: 00
VF offset: 1, stride: 1, Device ID: a824
Supported Page Size: 00000553, System Page Size: 00000001
Region 0: Memory at 00000000bdb10000 (64-bit, non-prefetchable)
VF Migration: offset: 00000000, BIR: 0
Capabilities: [3a4 v1] Data Link Feature <?>
Kernel driver in use: nvme
Results
$ sudo ./pcilmr -T -V 52:00.0
Link 4f:5.0 -> 52:0.0
Negotiated Link Width: 4
Link Speed: 16.0 GT/s = Gen 4
Available receivers: Rx(A) - 1, Rx(F) - 6
Receiver = Rx(A)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 0
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 0
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 63
Number of Voltage Steps: 127
Max Timing Offset: 50
Max Voltage Offset: 12
Max Lanes: 0
Receiver = Rx(F)
Error Count Limit = 4
Parallel Lanes: 1
Independent Error Sampler: 1
Sample Reporting Method: 0
Independent Left and Right Timing Margining: 1
Voltage Margining Supported: 1
Independent Up and Down Voltage Margining: 1
Number of Timing Steps: 31
Number of Voltage Steps: 127
Max Timing Offset: 50
Max Voltage Offset: 19
Max Lanes: 3
Results:
Link 4f:5.0 -> 52:0.0:
Rx(A) Lane 0 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 75.6 mV - 80st LIM, D 73.7 mV - 78st LIM
Rx(A) Lane 1 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 78.4 mV - 83st LIM, D 80.3 mV - 85st LIM
Rx(A) Lane 2 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 76.5 mV - 81st LIM, D 80.3 mV - 85st LIM
Rx(A) Lane 3 - Bad T 15.9% UI - 9.92ps - 20st LIM, U 80.3 mV - 85st LIM, D 78.4 mV - 83st LIM
Rx(F) Lane 0 - Perfect L 38.7% UI - 24.19ps - 24st LIM, R 38.7% UI - 24.19ps - 24st LIM, U 190.0 mV - 127st THR, D 190.0 mV - 127st THR
Rx(F) Lane 1 - Perfect L 41.9% UI - 26.21ps - 26st LIM, R 41.9% UI - 26.21ps - 26st LIM, U 190.0 mV - 127st THR, D 190.0 mV - 127st THR
Rx(F) Lane 2 - Perfect L 38.7% UI - 24.19ps - 24st LIM, R 37.1% UI - 23.19ps - 23st LIM, U 190.0 mV - 127st THR, D 190.0 mV - 127st THR
Rx(F) Lane 3 - Perfect L 38.7% UI - 24.19ps - 24st LIM, R 37.1% UI - 23.19ps - 23st LIM, U 190.0 mV - 127st THR, D 190.0 mV - 127st THR