Created
October 6, 2018 15:41
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| from mcu import mem32 | |
| # PWM clock manager | |
| CLK_GND = const(0) | |
| CLK_OSC = const(1) | |
| CLK_PLLA = const(4) | |
| CLK_PLLC = const(5) | |
| CLK_PLLD = const(6) | |
| CLK_HDMI = const(7) | |
| def set_CM_CTL(reg): | |
| mem32[0x201010a0] = 0x5a000000 | reg | |
| def set_CM_DIV(divi, divf=0): | |
| mem32[0x201010a4] = 0x5a000000 | (divi << 12) | divf | |
| def PWM_clock_config(src, divi, divf=0, mash=1): | |
| set_CM_CTL(mem32[0x201010a0] & 0xffef) # disable clock | |
| while mem32[0x201010a0] & 0x0080: # wait for the end of clock | |
| pass | |
| set_CM_CTL(src | ((mash & 3) << 9)) # set clock source and mash | |
| set_CM_DIV(divi, divf) | |
| set_CM_CTL(mem32[0x201010a0] | (1<<4)) # enable clock |
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