Created
October 28, 2018 12:23
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# Set the EN bit to enable the PCM block. | |
mem32[CS_A] = 1 | |
# Set all operational values to define the frame and channel settings. | |
mem32[MODE_A] = 1<<24 | 1<<22 | 1<<20 | 31<<10 | 16 | |
mem32[TXC_A] = 1<<30 | 1<<20 | (16-8)<<16 | 1<<14 | 17<<4 | (16-8) | |
# Assert RXCLR and/or TXCLR wait for 2 PCM clocks to ensure the FIFOs are reset. | |
mem32[CS_A] |= 1<<4 | 1<<3 | |
# The SYNC bit can be used to determine when 2 clocks have passed. | |
mem32[CS_A] |= 1<<24 | |
while (mem32[CS_A] & 1<<24) == 0: | |
pass | |
# Set RXTHR/TXTHR to determine the FIFO thresholds. | |
mem32[CS_A] |= 3<<5 | |
# If transmitting, ensure that sufficient sample words have been written to PCMFIFO | |
# before transmission is started. | |
for i in range(32): | |
mem32[FIFO_A] = 0 |
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