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Tolerate Glitches on Bus Transitioning between Stable States

This example shows how to use Verilog inertial delay modeling to avoid dynamic hazards on a bus changing from one stable state to another, such as when caused by differences in delays of individual bits.

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LFSR based implementation of CRC-8-CCITT

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API Doc Generators for Python Code

• https://wiki.python.org/moin/DocumentationTools
• https://pdoc3.github.io/pdoc/doc/pdoc/#pdoc&gsc.tab=0
• https://github.com/PyCQA/pydocstyle - pydoc style checker
• testing examples
  • https://github.com/pdoc3/pdoc/blob/master/pdoc/test/example_pkg/__init__.py

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SystemVerilog: Display eventual observed bus value

Problem: For a bus, ignore delta cycle changes and report only the eventual value at the and of the current time (slot).

`timescale 1ns/1ps

module tb;

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References to Titles/Headings in reStructuredText (RST)

In RST, one can easily refer to a title/heading (or more generally to a section start, which the heading really is) by using its text as a reference. For example:

... some text and then reference to `My Heading`_ ...

My Heading
~~~~~~~~~~

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Python Prductivity Tips

UML Class Diagrams

Pyreverse (part of Pylint):

• natively supports .dot (GraphViz), UMLet and PlantUML outputs
• useful options

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Distributing total into evenly sized integers

A snippet showing how to distribute even integral weights (e.g. percantage).

from random import randrange

def distribute(n,total=100):

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Customizing reStructuredText (rst) for Domain-specific Syntax

• document tree
  • created by a Parser component (i.e. from reStructuredText input)
  • manually constructed
• docutils components

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OpenSTA

OpenSTA is an open-source STA tool by Parallax (hence a.k.a. Parallax STA/Static Timing Analyzer). User Manual is part of the repository.

Build

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Custom Coverpage with LaTeX memoir

Example showing use of custom cover page with memoir class of article class option. There are some few "tricks" to yield the desired effect.