Functions in Bash may use local variables to create a local scope. For example:
$ function f0 { local a; a=0; echo "f0(a)=$a"; }
$ a=x;
$ echo "a=$a"; f0; echo "a=$a"
a=x
f0(a)=0
brabect1
brabect1
/ bash_local_vars.md
Last active
February 9, 2017 10:36
Discusses an interesting attribute of local variables in Bash.
foreach v [info vars] { if {![array exists $v]} { puts "$v = [set $v]"; } else { puts "$v is array"; } }
brabect1
/ uvm_sequences.md
Last active
June 21, 2024 11:58
Summarizes understanding of UVM sequences.
- inheritance: uvm_transaction <-- uvm_sequence_item <-- uvm_sequence_base <-- uvm_sequence#(type REQ=uvm_sequence_item, type RSP=REQ)
- concepts
- Sequences encapsulate user-defined procedures that generate multiple uvm_sequence_item-based transactions. [1]
- uvm_sequence_item: The uvm_sequence_item is the base class for user-defined transactions that leverage the stimulus generation and control capabilities of the sequence-sequencer mechanism. [1]
This gist is to compare some of existing open-source RV cores. The list is by no means meant to be comprehensive. Also, do check the list at RISC-V Foundation site, which may be more up to date.
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/ pulp_zeroriscy_notes.md
Last active
January 20, 2019 09:32
Collection of notes on [zero-riscy](https://github.com/pulp-platform/zero-riscy) RISC-V implementation.
brabect1
/ riscv_debug_module_v11.md
Last active
January 16, 2025 09:51
Describes implementation of RISC-V Debug Module (primarily as per Debug Spec. v0.11).
This gist discusses implementation of a Debug Module (DM) primarily per RISC-V Debug Specification v0.11. The core ideas, though, apply to Debug Specification v0.13. Information presented here come from various sources, but mostly from Debug Specs, riscv-isa-sim and from reverse engineering e200_opensource. Relevant source of information is also riscv-openocd.
RISC-V Foundation established a debug task group to propose and standardize mechanisms for external debugging of RISC-V (RV) cores. This effort resulted in drafting a RISC-V External Debug Supprt specification, early [v0.1
brabect1
/ multithreads_driving_verilator.md
Created
December 30, 2018 19:01
Simple example of using a Verilator model from multiple threads.
Most of the time, a verilated Verilog/SystemVerilog can be driven from a single threaded test. And if not, SystemC may come to rescue.
There can be situations, where a true multithreaded test is needed. An particular example is connecting a debugger to a Verilator model of a CPU. You will need one thread to interface GDB (maybe through other layers such as OpenOCD) and another thread generating a "normal" stimuli to the CPU model (reset, clock, etc.).
brabect1
/ _sta_async_counter.md
Last active
February 2, 2024 00:40
Shows how to constrain an asynchronous counter. #sta #doc
This work is licensed under a Creative Commons Attribution 4.0 International License.
[1] Why am I Getting UITE-461 Messages and Zero Source Latency?, Solvent article No. 020373, last modified 12/13/2016, https://solvnet.synopsys.com/retrieve/020373.html