Created
March 13, 2018 00:40
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diff --git a/lib/Target/AVR/AVRISelLowering.cpp b/lib/Target/AVR/AVRISelLowering.cpp | |
index 7ac8a136e6b..4f7d3d6a815 100644 | |
--- a/lib/Target/AVR/AVRISelLowering.cpp | |
+++ b/lib/Target/AVR/AVRISelLowering.cpp | |
@@ -1371,16 +1371,12 @@ AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, | |
MachineFunction &MF = DAG.getMachineFunction(); | |
unsigned e = RVLocs.size(); | |
- // Reverse splitted return values to get the "big endian" format required | |
- // to agree with the calling convention ABI. | |
- if (e > 1) { | |
- std::reverse(RVLocs.begin(), RVLocs.end()); | |
- } | |
- | |
SDValue Flag; | |
SmallVector<SDValue, 4> RetOps(1, Chain); | |
// Copy the result values into the output registers. | |
- for (unsigned i = 0; i != e; ++i) { | |
+ // Reverse loop to get the "big endian" format required | |
+ // to agree with the calling convention ABI. | |
+ for (int i = (e - 1); i < 0; --i) { | |
CCValAssign &VA = RVLocs[i]; | |
assert(VA.isRegLoc() && "Can only return in registers!"); | |
diff --git a/test/CodeGen/AVR/rust-avr-bug-92.ll b/test/CodeGen/AVR/rust-avr-bug-92.ll | |
new file mode 100644 | |
index 00000000000..f93bf7a152d | |
--- /dev/null | |
+++ b/test/CodeGen/AVR/rust-avr-bug-92.ll | |
@@ -0,0 +1,6 @@ | |
+; RUN: llc < %s -march=avr | FileCheck %s | |
+ | |
+define { i8, i32 } @chapstick() { | |
+start: | |
+ ret { i8, i32 } zeroinitializer | |
+} | |
\ No newline at end of file |
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