KOReader RISC-V Compilation (First-pass)

There was a total of about five changes that were necessary to compile KOReader for riscv64 on Framework Laptop 13 with Deepcomputing RISC-V Mainboard v1 with SiFive U74 RISC-V cores (RVA22). This is a first pass to see if it would compile, so these changes are minimal and will need be improved.

SIMD

In the file at base/Makefile.defs:

diff --git a/Makefile.defs b/Makefile.defs
index ad0c9d75..aec4d1db 100644
--- a/Makefile.defs
+++ b/Makefile.defs
@@ -610,7 +610,7 @@ else ifeq ($(TARGET), macos)
     TARGET_CFLAGS = -mtune=generic
   endif
 else ifdef EMULATE_READER
-  TARGET_CFLAGS = -march=native
+  TARGET_CFLAGS = -march=rv64gc
 endif
 
 # Some of our deps require C11 & C++17 (`if constexpr (…)`) support.
@@ -733,7 +733,7 @@ CXXFLAGS := $(strip $(CXXFLAGS))
 LDFLAGS := $(strip $(LDFLAGS))
 
 # NOTE: We generally want SIMD/ASM juicy stuff everywhere
-WANT_SIMD=1
+WANT_SIMD=
 # ... but on ARM targets that are not NEON capable, that obviously won't fly...
 ifneq (,$(filter -march=arm%,$(CFLAGS)))
   # We're on ARM.

The SIMD extensions of RISCV are not yet available and these need to be disabled, this is mostly relevant for building the libjpeg-turbo library (https://github.com/libjpeg-turbo/libjpeg-turbo). The P extension is under development and could be used at a later date: https://riscv.atlassian.net/browse/RVS-1135 Also the march=native was not picking up the host arch and need to be specified.

CHMLib

In the file at: base/thirdparty/kpvcrlib/crengine/thirdparty/chmlib/src/chm_lib.c:

diff --git a/thirdparty/chmlib/src/chm_lib.c b/thirdparty/chmlib/src/chm_lib.c
index 0b11da7d..70090512 100644
--- a/thirdparty/chmlib/src/chm_lib.c
+++ b/thirdparty/chmlib/src/chm_lib.c
@@ -169,7 +169,7 @@ typedef unsigned long long      UInt64;
 
 /* x86-64 */
 /* Note that these may be appropriate for other 64-bit machines. */
-#elif __x86_64__ || __ia64__ || __aarch64__
+#elif __x86_64__ || __ia64__ || __aarch64__ || (defined(__riscv) && (__riscv_xlen == 64))
 typedef unsigned char           UChar;
 typedef short                   Int16;
 typedef unsigned short          UInt16;

Small patch to recognize riscv64 for typedefs.

LuaJIT

In the file at base/thirdparty/luajit/CMakeLists.txt:

diff --git a/thirdparty/luajit/CMakeLists.txt b/thirdparty/luajit/CMakeLists.txt
index 8a929df0..e03bde9c 100644
--- a/thirdparty/luajit/CMakeLists.txt
+++ b/thirdparty/luajit/CMakeLists.txt
@@ -95,8 +95,8 @@ endif()
 append_tree_install_commands(INSTALL_CMD src/jit jit)
 
 external_project(
-    DOWNLOAD GIT 659a61693aa3b87661864ad0f12eee14c865cd7f
-    https://github.com/LuaJIT/LuaJIT
+    DOWNLOAD GIT e9c0b90b64df769a53fda125c4fff31557091762
+    https://github.com/plctlab/LuaJIT
     PATCH_FILES ${PATCH_FILES}
     PATCH_COMMAND ${PATCH_CMD}
     BUILD_COMMAND ${BUILD_CMD}

This is the most signifigant change. It was necessary to switch to a branch of luajit that has implemented support for RISC-V at: https://github.com/plctlab/LuaJIT There is a pending pull request to add support at: LuaJIT/LuaJIT#1267

X11

In the file at base/thirdparty/sdl3/CMakeLists.txt:

diff --git a/thirdparty/sdl3/CMakeLists.txt b/thirdparty/sdl3/CMakeLists.txt
index 560ca3a7..421748cf 100644
--- a/thirdparty/sdl3/CMakeLists.txt
+++ b/thirdparty/sdl3/CMakeLists.txt
@@ -33,6 +33,8 @@ list(APPEND CMAKE_ARGS
     -DSDL_LIBTHAI=OFF
     -DSDL_SENSOR=OFF
     -DSDL_TRAY=OFF
+    -DSDL_X11_XSCRNSAVER=OFF
+    -DSDL_X11_XTEST=OFF
 )
 if(USE_SDL STREQUAL "builtin")
     list(APPEND CMAKE_ARGS

This may or may not be related to RISC-V and rather related to running Wayland and not having x11 development files installed.

Cluacov

In the file at base/thirdparty/spec/cluacov/CMakeLists.txt:

diff --git a/thirdparty/spec/cluacov/CMakeLists.txt b/thirdparty/spec/cluacov/CMakeLists.txt
index d4d77e82..f4091725 100644
--- a/thirdparty/spec/cluacov/CMakeLists.txt
+++ b/thirdparty/spec/cluacov/CMakeLists.txt
@@ -1,4 +1,4 @@
 spec_rock(
     https://luarocks.org/manifests/luarocks/cluacov-0.1.4-1.src.rock
-    076273d593b0aa95666f1d3238d6549e
+    ac3cb548ea1025cbc7a60e3fa9c85a8a
 )

This also includes modifying the cluacov-0.1.4-1.src.rock file. You will likely need to run a build for it to fail and then replace the file. It includes .h header files that need to be updated from files from the earlier LuaJIT update with RISC-V support. You can achieve this by unzipping the .rock file, copying the header files, rezipping it, and replacing the .rock file. As it's already downloaded it won't be downloaded again and replaced, the md5 has will need to be updated though. The can be verified using the md5sum command.

These are the files that need to be replaced (mainly lj_arch.h):

cluacov/src/cluacov/lj2/lj_arch.h
cluacov/src/cluacov/lj2/lj_def.h
cluacov/src/cluacov/lj2/lj_gc.h
cluacov/src/cluacov/lj2/lj_obj.h

They can be copied from base/thirdparty/luajit/build/downloads/sources/src. The src directory will likely not exist yet, it is a sparce git repository. You can disable the sparce checkout with git sparse-checkout disable and proceed with copying the files with the same name.

braydonf/koreader-riscv.md

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